DP83TD510E: Sensitivity to Indirect ESD Discharge to Plane

Above, I meant media converter, not repeater.  Apologies.

Cyrus

Hi Cyrus,

Thank you for getting in touch with us.

What is the ESD voltage used for testing?

The link dropping and recovering by itself (Class B) is not perceived as fail. IEC61000-4-2 shows Class B as acceptance criteria for ESD testing.

Is ESD performance of Class A, a requirement for your system?

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Regards,
Gokul

Hello Gokul,

Thanks for the quick reply.

+/4KV is what I am using for discharge to the plane.

I need Class A.  The product is for a hazardous industrial environment.  Communication disruption would be very bad and EMI levels are high.

I have 2 thoughts about improving the situation.

1. Use the DP83TD510E as RMII Master and setup a circuit to start up the DP83822 after the DP83TD510E.  I'm not sure how much of a delay is needed between starting up the 2 PHYs, so I would need to know that.  
2. Use the RGMII Media Converter mode instead of RMII.  The DP83TD510E datasheet says, "With RGMII Mac, mac interface clock runs
   at 2.5MHz and will dissipate less power and offer improved signal integrity."  Could RGMII be more tolerant of EMI?
   

It makes me nervous trying to solve this issue without knowing what is really going wrong.  Can you provide any insight into what part of the circuit is sensitive to this test?  Is it the RMII communications and/or clock?

If you have any suggestions for improvements I would appreciate them.

Thanks for your help,

Cyrus

Hi Cyrus,

Please let me have a discussion with the team on this. I'll get back to you by end of Tuesday.

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Regards,
Gokul.

Hi Cyrus,

The device failing in RMII slave for APL and passing in RMII master for APL suggest some sensitivity with respect to 50MHz clock input to XI pin. We might have to go through reviews of the clock scheme and routings first and debug cycle later to prove the hypothesis.

In RGMII mode, the performance will be better as the clock speed is still 25MHz. Careful layout of the crystal might just make Class A pass.

Please let me know your thoughts.

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Regards,
Gokul.  

Hello Gokul,

I did some testing on my PCB that supports the idea that the DP83TD510E XI pin is sensitive to the ESD testing I'm doing.

If I made the DP83TD510E RMII Master and delayed the startup of the DP83822 that would put a 25MHz crystal on the DP83TD510E XI and XO.  Would that be an equally good approach to RGMII? 

My current PCB layout uses RMII.  RGMIII would add a good number of traces between the PHYs and be more work to revise the layout.  However, if RGMII is more likely to fix the issue and/or be more robust overall, then I would change to RGMII.

If the DP83TD510E as RMII Master approach is just as good as the RGMII approach, then I will go with RMII.  I just would need an idea of how long to let the DP83TD510E startup and get a stable 50MHz clock going to the DP83822 before starting up the DP83822.

I would appreciate your advice on which approach is more robust.

Best regards,

Cyrus

Hi Cyrus,

When DP83TD510E is used as RMII Master, the device DP83822 is used in RMII Slave which now takes 50MHz clock input.
The device DP83822 is also not tested for Class A performance and I am not sure whether there is some sensitivity with 50MHz clock input with the DP83822 PHY.
You can be confident that this configuration of RMII master and slave has no problems across boards/devices if you do the testing at a higher voltage (let's say 4.5kV).

For the Class A performance, we anyway have to rely on the testing on your side and it doesn't matter if it is RGMII or RMII if it passes on your setup with some margin.

Incase you want to go through the path of RMII, can you please share the schematic and layout of the board? I can take a look and let you know if some improvements can be done.

Please let me know if you need more details.

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Regards,
Gokul.

I marked it as resolved.  Thanks Gokul.

Cyrus