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DP83867IR: Layout guideline

Taketo Sato
Genius 10325 points
Part Number: DP83867IR

Hello team,

I have questions about DP83867IR RGMII layout guideline.

Its datasheet 9.2.2.1.1, there is a guideline of skew for TXD and RXD and it should be less than 60 mil.

  • Don't we have any skew requirement for its clock?
  • We can adjust clock skew in 0.25-ns increments by register. Is there target value for the clock skew?


Also, there is a guideline that trace length should be as short as possible and less than 2 inches is recommended.

  • Is there trace length requirement between PHY and RJ45?

Best regards,

  • +1
    TI__Mastermind 19250 points

    Hi Taketo-san,

    Yes, we have a skew requirement on TXD and RXD.

    The skew requirement between clock and data according to the RGMII standard is 2ns (typical). The skew can be generated internally in steps of 0.25ns on RX pins and TX pins independently.

    When we are transmitting (on RXD pins) in align mode, it is recommended to not have a skew between RX_CLK and RX_D routings.
    When we are transmitting in shift mode (internal delay mode), we can adjust the clock skew in steps of 0.25ns- depending on the routings skew between RX_CLK and RX_D.
    Please note that there should be minimal skew between each of RX_D[3:0]. We can skew the clock skew in steps of 0.25ns, but we can't skew each of the data lines independently.

    When we are receiving (on TXD pins) in align mode, it is recommended to not have a skew between TX_CLK and TX_D routings.
    When we are receiving in SHIFT mode, we can adjust the clock skew in steps of 0.25ns depending on the routings skew between TX_CLK and TX_D. Please note that there again should be minimal skew between each of TX_D[3:0].

    On MDI side (between PHY and RJ45 , we propose the trace length on case-to-case basis. As a rule of thumb, you can try to keep the trace length to less than 2 inch between PHY and magnetic and less than 1 inch between magnetic and RJ45.

    Please let me know if you need more details.

    --
    Regards,
    Gokul.

  • 0 in reply to Gokul Koraganji
    TI__Genius 10325 points

    Hello Gokul-san,

    Thank you for your comments.

    2ns(typ) skew is needed between clock and data? and is my below understanding correct?

    • In aligned mode, the 2ns skew/delay is automatically added internally, so no need to have a skew between RX(TX)_CLK and RX(TX)_D routings.
    • In shift mode, 2ns skew by routing or by register adjustment is required. 

    Best regards,

  • +1 in reply to Taketo Sato
    TI__Mastermind 19250 points

    Hi Taketo-san,

    Yes, the skew between clock and data lines should be 2ns(typ).

    For RX lines, in align mode, there is no skew between RX_CLK and RX_DATA lines. The 2ns delay should be taken care by the MAC. In shift mode, there is a delay generated internally before transmission and skew is seen between RX_CLK and RX_DATA and there is no need to add any routing skew.

    For TX lines, in align mode, there is no internal skew added between TX_CLK and TX_DATA. The PHY expects that MAC transmits with a delay between TX_CLK and TX_D lines. In shift mode, there is an internal skew generated, so there is no need for MAC to skew the clock & data and no need to add any routing skew.

    Please let me know if you need more details.

    --
    Regards,
    Gokul.

  • 0 in reply to Gokul Koraganji
    TI__Mastermind 19250 points

    Hi Taketo-san,

    Please let me know if there the details are sufficient. If so, can you please mark the query resolved?

    --
    Regards,
    Gokul.