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Original question:

DP83867IS: questions about T1

DP83867IS: Datasheet queries (sequence and power saving)

Kazuki Itoh
Genius 10720 points
Part Number: DP83867IS

Hi team,

Could you please help me to answer datasheet questions below?

1. What is the maximum allowed value of T1, T2 and T3 in the datasheet 7.6?
(I recognize T1 requirement is already given in this thread. How about T2 and T3?)

2. After releasing reset, in order to avoid unintentional link-up before programming the register setting, my customer would like to use the POWER_DOWN pin.
Should POWER_DOWN pin be asserted low before releasing the reset signal?
Also, does POWER_DOWN pin low-to-high have any timing requirement after releasing the reset?

3. In datasheet 8.6.22, Which is the best LED_GPIO_SEL and LED_2_SEL configuration to save the power consumption? My customer will use only LED_0 and LED_1 pin.

4. In datasheet 8.6.96, Does disabling CLK_O_DISABL help to save power consumption?

5. In datasheet 8.6.97 GPIO Mux Control Register, which is the best GPIO_1_CTRL and GPIO_0_CTRL configuration to save the power consumption? My customer won't use GPIO_0 and GPIO_1.

6. Could you let me know the recommended register setting to save the power consumption? My customer would like to turn off as many circuit blocks as possible to save the power.

7. Is it OK to stop MDC clock supply when not accessing MDIO interface?

8. After stopping the MDC clock and then I want to access MDIO again, is it good if I supply MDC clock again? Does it better to wait for some time before accessing MDIO after supplying MDC clock ?

Regards,

Itoh

  • 0
    TI__Mastermind 39755 points

    Itoh-san,

    There is no maximum specified value for T1, T2, T3 in datasheet section 7.6.

    We do not have this characterized, but we suspect PHY's POR will take precedence before PWDN can even register an assertion. We do not have any data regarding PWDN timing.

    A good majority of your questions are regarding power savings, so I will address them all here. Outside of adjusting speed (system requirement) and supplying a 1.8V supply, configurations that disable CLKOUT and GPIO's will technically save power, but will be very minimal compared to speed and supply adjustments. A good majority of the PHY's power consumption is due to its normal operation, and therefore there aren't a lot of power savings to be had by disabling/modifying CLKOUT/GPIO pin states.

    It is perfectly fine to stop MDC clock whenever SMI access is not needed.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    TI__Genius 10720 points

    Hi Gerome-san,

    Thank you for your support.

    I don't understand your answer for #2.

    > "We do not have this characterized, but we suspect PHY's POR will take precedence before PWDN can even register an assertion."

    Could you kindly answer again with more straightforward expression?

    Regards,

    Itoh

  • 0 in reply to Kazuki Itoh
    TI__Mastermind 39755 points

    Hi Itoh-san,

    Thank you for your query.

    To further explain, when Reset is released and the PHY is going through its process of getting out of that state, the PWDN pin assertion will not register and take effect until after the PHY is out of Reset state. Therefore, it should be okay to assert low before releasing Reset signal. However, this has not been tested to confirm.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    TI__Genius 10720 points

    Hi Gerome-san,

    About the PWDN assertion timing after reset deassertion, you said, you don't have any data regarding PWDN timing.

    My customer thinks that PWDN should be assert high at least after T2=120ns (Hardware configuration latch-in time from the deassertion of RESET).

    Could you please comment?

    Regards,

    Itoh

  • +1 in reply to Kazuki Itoh
    TI__Mastermind 39755 points

    Itoh-san,

    Again, we do not have any data regarding PWDN timing. However, the times you are seeing in section 7.7 are the times for how long it would nominally take for the PHY to sample the strapping voltage (T2) and then transition those strapping pins to regular operation (T3). Isn't your customer trying to program the PHY while in PWDN mode to avoid unintentional link up? If that is the case, this would have to be a little bit after T1, as that is when MDC/MDIO access is ready post-reset. Once your customer has finished register programming, then they should release PWDN. 

    Sincerely,

    Gerome