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Hi Team, seeking some help.
The load resistors are set so IOH/IOL doesn't exceed +/-1mA at maximum output voltages. The key is CC compensation capacitor. Ideally R1 x CC = R2 x Cin. since 20pF is the maximum RTG4 MSIOD input capacitance, I scaled the ratio for Cin = 15pF. The value of CC needs to be verified by test in the lab. It is the only "critical" selection for optimal waveform profile. I used 1% resistors, but they could easily be 5%. the clock will be 40MHz, the worst case we need is 80MHz.
ELECTRICAL CHARACTERISTICS page 5 see below, VOHmin (@IOH = -4mA) = 2.4V and VOLmin (@IOL = 4mA) = 0.4V. this is the right parameters for the worst case analysis
or I need to use figure 7 & 8 for the worst case analysis. for example, i need the output to be 2.5V from the figure the output current should be around 16mA. can you please confirm if i need to use +/-4mA or 16mA for worst case analysis. see below
FPGA input Level see below...
below we add voltage divider between your IC and FPGA. "voltage level shifter" I need to make sure my solution dose not affect your IC on worst case analysis.
Hoping for your kind assistance.
Thank you.
-Mark
