Hello TI Support,
I'm having some weird stuff happening on my I2C bus, and I'm wondering if it's related to clock stretching on the TPS65988. My I2C bus has an MCU and two TPS65988 chips (connected to I2C1) on it and nothing else. Both chips are configured with I2C1 as a slave. I wrote a simple app on the MCU to pull each PD controller out of reset and then poll the MODE register (0x3) every 10 seconds. The procedure I'm following for the register read is as follows:
I2C Start with address and write bit -> write 0x3 (mode register) -> I2C repeated start with address and read bit -> 5 byte read -> stop.
The data coming through is exactly as expected, but the timing for the I2C bits is off, specifically for the first start byte. Here is a screenshot of the entire transaction on my oscilloscope:
Zooming in at t=0, we see that just the first 7 bytes (address) are sent, and then SCL remains low for a while.
There's a long delay where SCL is low, and the 8th bit (write bit) isn't sent until the 3.2 ms mark:
You can see that the data is written immediately after, without any delay. There is then a short delay before the read transaction starts, but that transaction is much quicker:
Sometimes, the delay in the first write transaction is so long (~10 ms) that my MCU thinks the bus has timed out, and it will throw an error. This is causing some problems in my application.
I'm wondering what the possible causes are for this delay? I saw in the TPS65988 datasheet (section 8.3.12.2) that it does support clock stretching. It mentioned though that clock stretching usually occurs before the ACK bit. I'm seeing it before the write bit though which seems strange. Is this possible behavior for the TPS65988? If so, is there anything I can do to make release the clock faster?
Best regards,
Cory
