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TLK1501 QUESTION

Brian Holub
Prodigy 10 points
Other Parts Discussed in Thread: CDCLVC1104, TLK1501

Hi,

I have a board that I made that contains four TLK1501s whose GTX_CLK inputs are driven by a CDCLVC1104 clock buffer. The buffer is driven by a Virtex 6 output signal that is located on an eval board that comes up thru a FPGA Mezzanine connector. The clock is single ended and is 40 MHZ.

The TLKs are each  hooked up to their own SFP modules. If I connect a short fiber jumper from the TX port to the RX port of channel A, the link works properly and data is passed on to the RX side perfectly.  If I do the same for Channel B it works as well. But if I connect the TX of port A to the RX of port B or vice versa,  the links do not work and the RX_ER control lines toggle. Could this problem be due to jitter on the GTX_CLK ? or something else which I am missing? What's the difference if the TX signal is originating from the same channel  as the RX or from a channel next to it?

Thanks,

Brian

  • 0
    TI__Expert 7850 points

    Hello Brian,

    In situations such as the one you described, often it is the reference clock jitter that can lead to various issues.  Do you know if the reference clock being provided to the serdes meets the 40ps p-p jitter requirement?  We would suggest looking at the clock output spec of the FPGA to determine if the jitter is in line with what the TLK1501 requires.  If possible, you  may want to source the clock from a known good source (i.e. meets clock jitter spec) such as a crystal oscillator and see if the link between A and B device can be established. 

     

    Thanks,

     

    Atul Patel

    Texas Instruments