DSLVDS1001: Jitter /Phase Noise Spec

Stephen Thomas

Part Number: DSLVDS1001

Hello,

We are having a Serdes interface which requires a reference differential clock 101MHz with maximum jitter +/-10ps (Peak to Peak Jitter) . The single ended clock source with low jitter/phase noise spec is identified, however to convert it into an differential out we are considering the DSLVDS1001. So i would like to know if this device is suitable for such an application, and if so is there any additive phase noise or some jitter increase may occur which may violate the serdes chip spec.

Any suggestion will be helpful.

Thanks

Stephen

over 3 years ago

0 Malik Barton57 over 3 years ago

TI__Guru 64326 points

Hi Stephen,

I believe DSLVDS1001 can meet this spec. The added jitter for this device should be small the major source of jitter will com from the PCB design loses.

0 Stephen Thomas over 3 years ago in reply to Malik Barton57

Intellectual 710 points

Hi Malik,

Thank you for the reply. Is there any estimate (say ps or fs) for the added jitter for this device. I see for the higher operating speed drivers some jitter spec is usually available in datasheet but for this particular speed grade ( i.e. 400Mbps range) jitter information seems not that common.

0 Malik Barton57 over 3 years ago in reply to Stephen Thomas

TI__Guru 64326 points

Hi Stephen,

Unfortunately I do not have this specific spec for this device.

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DSLVDS1001: Jitter /Phase Noise Spec