Dear Team,
We have measured Tpv which follow datasheet figure7-2/7-3 and note B(0.7 × VCC on SCL to 50% I/O (Pn) output).
But the result is out of datasheet spec, could you share your comments with us?
Regards,
Ben
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Dear Team,
We have measured Tpv which follow datasheet figure7-2/7-3 and note B(0.7 × VCC on SCL to 50% I/O (Pn) output).
But the result is out of datasheet spec, could you share your comments with us?
Regards,
Ben
Hi Ben,
Something about the yellow waveform looks a bit strange to me. It seems like prior to the measurement the signal is transitioning from HIGH to LOW, then only 3 clocks it transitions from low to high. For our device, we require atleast 9 clock cycles to transition from low to high or high to low. I'm a bit skeptical this is the Pn pin.
From my testing/validation of this parameter, I recall the output actually changes at around 30% of the of the SCL ACK pulse. So usually the tpv time is actually negative.
Can you redo your measurement with the SDA/SCL pins and double check CH1 is indeed connected to the p-port.
-Bobby