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DS90UB960-Q1: interrupt question

Sherry Liang
Genius 10255 points
Part Number: DS90UB960-Q1

Dear team,

My customer enables RX port interrupt by setting 0xD9 &0x23. When one fault condition appears, for example, ESD test, INTB will report the fault to SOC. When 960 detect the error frame, it still sends this error frame to SOC. Then what is the sequence between SOF/start of frame of this error frame and INTB? First SOF, then INTB? Or first INTB, then SOF? 

Thanks & Best Regards,

Sherry

  • 0
    TI__Mastermind 28240 points

    Hi Sherry,

    Since the customer has set reg 0xD9 = 0x23, then they are enabling interrupts for LOCK_STS, PORT_PASS, and LINE_CNT_CHG. 

    The UB960 has an adaptive equalization filter and a CDR circuit at each RX Port to track and recover the incoming serial data stream. The SER will continuously send an encoding sequence to the DES, across multiple 40-bit Forward Channel frames. The DES will check the encoding sequence for errors. If there are errors, then the DES declares that LOCK has not been established and the LOCK and PASS statuses will be updated accordingly. Once LOCK and PASS statuses are changed, the INTB pin will be triggered for an interrupt. If there are any errors, then LOCK will be lost and then an interrupt on the INTB pin will be generated.

    For UB960 also receives video from its connected SER one line at a time. Each RX port has a line buffer, which can hold up to 2 lines of video data, before being forwarded to an output port. For each video frame received, the DES will count the number of video lines in a frame. Any long packet will be counted as a video line. Between SOF and EOF, lines will be counted. If the next count of lines between the next SOF and EOF is different from the previous count, the LINE_CNT_CHG interrupt will be triggered.

    Best,

    Justin Phan

  • 0 in reply to Justin Phan
    TI__Genius 10255 points

    Hi Justin,

    Thanks for your detailed reply!

    I will describe more background here. My customer failed the ESD test, so we recommend the software workaround to them. The whole workaround process is as below,

    Step 1. enable interrupt(

    Write 0X4C=0x0F  # write RX0/1/2/3

    Write 0XD8=0x07  

    Write 0XD9=0x75  

    Write 0x23=0x8F  # enable  INTB pin & RX0/1/2/3 port interrupt)

    Step 2. Once SOC detects INTB low signal, it will disable the interrupt (0x23=0x00);

    Step 3. Then SOC will discard current error frame and continue to show last frame with no error.

    Step 4. Clear fault register, then enable interrupt again(0x23=0x8F). These operation will be finished within 40ms/one frame.(frame rate=25Hz)

    Currently we encounter some issues on step 3. They don't know how to distinguish current frame and adjacent frame. Their operation is that once SOC detect the interrupt, it will compare INTB time stamp and SOF time stamp. Once INTB time stamp-40ms<SOF time stamp<INTB time stamp, they will take this frame as current frame. But there are still error frame displaying on the screen even though SOC detect the interrupt. It seems that they didn't discard error frame successfully.

    So we want to confirm with you one sequence question. When DES detect errors in this frame, it will report on INTB pin. How long does it take from error detection to INTB pin report? For this frame, which time stamp will firstly come to SOC, SOF or INTB? What is the maxim time difference between SOF and INTB?

    Thanks & Best Regards,

    Sherry

  • 0 in reply to Sherry Liang
    TI__Mastermind 28240 points

    Hi Sherry,

    I am not quite clear on what you mean by SOF, since each interrupt has different sources and will thus trigger INTB at different timings. Errors are not held in a frame, before being sent to the INTB pin. Once an error is detected, the INTB pin will be triggered almost instantaneously, with no significant delay in the system level.

    But it seems that you would need to clear the interrupt error flags, before re-enabling the interrupts. In that case, after disabling the interrupts (reg 0x23 = 0x00), you would need to clear the appropriate interrupt status registers, before re-enabling the interrupts (reg 0x23 = 0x8F).

    Interrupt status registers are cleared on read. See registers 0x4D and register 0x4E in the UB960 for the interrupt status registers that need to be read, in order to clear them.

    Best,

    Justin Phan 

  • 0 in reply to Justin Phan
    TI__Genius 10255 points

    Hi Justin,

    Sorry to forget explaining the SOF. SOF means start of frame.

    Thanks & Best Regards,

    Sherry

  • 0 in reply to Sherry Liang
    TI__Mastermind 28240 points

    Hi Sherry,

    In previous posts, you were talking about the SOF of an error frame, which we do not have. We mainly talk about SOF if we are talking about video data transfer over the cable link. That's where my main confusion was.

    For errors, there are different trigger sources, which will affect when INTB is triggered.

    Best,

    Justin Phan