DP83848-EP: RGMII Interface Throughput and clock

Rajat Singh

Part Number: DP83848-EP

Hi Team,

I am just curious to know in RGMII Interface how the 125Mhz Clock provide 1Gbps Throughput with 4 TX Line?How the exactly bit will transmit on Tx pair with clock?

TX_CLK and RX_CLK both work on 125Mhz in 1000Mbps case?

So in this case RGMII Total throughput will be 2Gbps?

1G from TX and 1G from RX right?

Q2-What will be the packet format in the case of 100Mbps?

ETH-Phy will generate some random Packet?

Can you please share some document to complete understanding of RGMII?

over 3 years ago

0 Hillman Lin over 3 years ago

TI__Mastermind 25955 points

Hi Rajat,

RGMII standard document online should have the detail on the specific questions.

Regards,

Hillman Lin

0 Rajat Singh over 3 years ago in reply to Hillman Lin

Prodigy 20 points

Hi Hillman,

I have searched a lot can you please share the link that will be great.

0 Hillman Lin over 3 years ago in reply to Rajat Singh

TI__Mastermind 25955 points

Hi Rajat,

848 PHY does not support the RGMII interface. It can only support up to 50MHz for RMII. If you want to learn more about RGMII, try this link: https://www.fpgakey.com/wiki/details/270. I am not sure if I understand your confusion correctly. RGMII interface data at both rising and falling edge instead of only rising edge and it has only 4 data path. so it can transfer data at 125*4*2= 1000 per clock cycle.

Regards,

Hillman Lin

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DP83848-EP: RGMII Interface Throughput and clock