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DS26F32MQML-SP: 3rd channel o/P is going low even though if i kept corresponding I/P channel as Open

Saranraj Rajasekar
Prodigy 50 points
Part Number: DS26F32MQML-SP

Dear Sir,

     I am using DS26F32MWRQMLV Quad Differential Line Receivers for one of my application  board. Here  i am facing an issue which is the o/p of third(+inc, -Inc) channel is getting low if i programmed my fpga as i am using this pin as ProgramB for FPGA. Initially we are not driving the 3rd channel I/P(Kept as open) so as per the datasheet , a fail-safe input/output relationship keeps the outputs high when the inputs are open. 

Initially the O/P of the 3rd channel is high, but after i programmed fpga it is going low even though i kept the i/P of 3rd channel is open. SO my fpga is resetting.

Thanks in advance

Saranraj R

  • 0
    TI__Guru 52062 points

    Hi Saranraj,

    Thanks for reaching out.

    Is the FPGA connected to connected to input 3 (+ In C/ - In C)? If yes have you verified what the bus differential voltage is at this point?

    Also are you only seeing the problem when you program the FPGA with program_B?  What does this do to change the device when interacting with the receiver? 

    Please let me know.

    Best,

    Parker Dodson