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DS90UB954-Q1: MIPI CSI TX timing registers and lane rate tuning

Abhishek Hegde
Prodigy 60 points
Part Number: DS90UB954-Q1

At the moment to test the interface between deserializer and MIPI CSI RX, I'm using "pattern generator" in deserializer.

Now I came across fine tuning feature in the forum that describes how to reduce 1.6Gbps lane rate upto 1.3Gbps using registers that are not documented in datasheet.
1) What about 800Mbps, Is it possible to fine tune this as well ? if yes, how  ?
2) Is it necessary to match the lane rate requirement for a display timing to CSI TX lane rate ?
"ex: 1080p 60fps RAW10 would require 371.25 Mbps/lane when using all 4 lanes, will it work if I choose 800Mbps lane rate or do I need to match it exactly"

In data sheet register description, CSI0_TCK_*, CSI0_THS*, CSI0_TPLX ( section 7.6.198 - 7.6.206 ), mentions these register values are automatically determined.
1) Is this applicable to pattern generation as well or only when using serializer( i.e RX port forwarding is enabled)
2) Is there any case when these registers need to be manually configured ? If yes, how to determine these values ?

  • 0
    TI__Mastermind 18755 points

    Hello,

    1. It is possible to select different CSI rates like 1.6Gbps. 800Mbps, 400Mbps, by selecting it in register 0x1F.

    2. I does not matter from our end as long as 800Mbps is enough to handle the video bandwidth.  However you will probably want to confirm the display vendor about what their product can tolerate.  I don't think it matters because frame start, line start, frame end, line end, are all transmitted in the same way regardless of speed.

    3. These timing registers are set automatically based on the speed you select, I would recommend you do not try to change them manually.  Patgen send CSI data at the speed you select.

    4. No.

    Regards,

    Nick