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DP83TG720R-Q1: How does 720 distinguish 2 level or 3 level?

Elec Cheng
Expert 7055 points
Part Number: DP83TG720R-Q1

Hi Expert,

I have several questions about strap pin.

  1. How does 720 distinguish 2 level or 3 level? Is there a condition where mode is different under 2 level or 3 level when a voltage is applied?
  2. Can we configurate RGMI TX/RX delay to any time?
  3. If I don't want to use wakeup function, how to deal with VSLEEP supply and WAKE/INH?

Thanks a lot for help!

BR,

Elec Cheng

  • 0
    TI__Mastermind 19250 points

    Hi Elec,

    720 has 3-level straps only on pins RX_CTRL, STRP_1. These straps are used for only PHY ADDR.
    Other pins have only 2-level straps.

    RGMII TX and RX delays have to be set according to the timing budget of the RGMII standard. You can refer to table 1 in https://www.ti.com/lit/an/snla243/snla243.pdf.
    It is better to use 2ns delay by default if there is no extra clock data skew added due to board routings, parasitic mismatch etc.

    When you are not using sleep mode, you can connect VSLEEP pin to VDDA3P3 and leave WAKE & INH floating.

    Please let me know if you need more details.

    --
    Regards,
    Gokul.