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DP83869HM: Ethernet PHY Address strapping

Mitch Rillema
Prodigy 10 points
Part Number: DP83869HM

Table 11 of the datasheet shows the PHY_ADD strap table for PHY_ADD3, PHY_ADD2, PHY_ADD1, and PHY_ADD0.   But the PHY_ADD is actually 5-bits wide.   How is the upper PHY_ADD bit controlled during power-up/reset?

 

DP83869HM High Immunity 10/100/1000 Ethernet Physical Layer Transceiver With Copper and Fiber Interface datasheet (Rev. A) (ti.com)

 

  • 0
    TI__Mastermind 19250 points

    Hi Mitch,

    Thank you for getting in touch with us.

    DP83869HM has support only for 4 bits of PHY_ADDR (Address support from 0x0 to 0xF). I see that there are some typos in the datasheet which I'll propose to get corrected in the next version of the datasheet.

    --
    Regards,
    Gokul.