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SN65DSI86: dsi don't display to monitor

Other Parts Discussed in Thread: SN65DSI86

Hi

because i alway get error message from TI 0xF1 and 0xF6

1.CHA_INVALID_LENGTH_ERR. When the DSI channel A packet processor detects an invalid transmission length

2.DPTL_UNEXPECTED_DATA_ERR. This field is set whenever a data token at in the video stream from DSI was found at an invalid time syntactically

And we had confirm with SOC vendor , they can transfer RGB color format.

Current status is that using TI internal color pattern will display pass. but use SOC to transfer DSI signal without display.

So what can i do to debug this issue.?

We try to bypass TI SN65DSI86 IC and connect to panel is ok.

list is my use command flow

i2cset -fy 2 0x2c 0x5c 0x01 b
i2cset -fy 2 0x2c 0x0d 0x01 b
i2cset -fy 2 0x2c 0xff 0x07 b
i2cset -fy 2 0x2c 0x16 0x01 b
i2cset -fy 2 0x2c 0xff 0x00 b
i2cget -fy 2 0x2c 0x5a
i2cset -fy 2 0x2c 0x0a 0x06 b
i2cset -fy 2 0x2c 0x10 0x26 b
i2cset -fy 2 0x2c 0x12 0x55 b

i2cset -fy 2 0x2c 0x94 0xe0 b
i2cset -fy 2 0x2c 0x0d 0x01 b
i2cset -fy 2 0x2c 0x5a 0x04 b
i2cset -fy 2 0x2c 0x93 0x30 b

i2cget -fy 2 0x2c 0x0a

i2cset -fy 2 0x2c 0x96 0x02 b

i2cset -fy 2 0x2c 0x96 0x0b b


i2cset -fy 2 0x2c 0x20 0x80 b
i2cset -fy 2 0x2c 0x21 0x07 b
i2cset -fy 2 0x2c 0x24 0x38 b
i2cset -fy 2 0x2c 0x25 0x04 b
i2cset -fy 2 0x2c 0x2c 0x2c b
i2cset -fy 2 0x2c 0x2d 0x00 b
i2cset -fy 2 0x2c 0x30 0x05 b
i2cset -fy 2 0x2c 0x31 0x00 b
i2cset -fy 2 0x2c 0x34 0x94 b
i2cset -fy 2 0x2c 0x36 0x24 b
i2cset -fy 2 0x2c 0x38 0x58 b
i2cset -fy 2 0x2c 0x3a 0x04 b
i2cset -fy 2 0x2c 0x5b 0x00 b
i2cset -fy 2 0x2c 0x3c 0x00 b
i2cset -fy 2 0x2c 0x5a 0x0c b
i2cset -fy 2 0x2c 0x59 0x1b b

  • Hi,

    Can you please share your panel EDID information? Have you used the spreadsheet in this link to generate the DSI86 register programming value?

    Addresses 0xF0 thru 0xF3 report errors associated with the DSI interface. Sometimes errors flags can be set at power-on or during start of the DSI stream. For this reason, it is recommended to clear flags by writing 0xFF and then reading back status flags. The bits which remain set are the errors which should be focused on. Typically errors set in these fields indicate signal integrity issues. Recommend verifying setup/hold meet DSI86 requirements. Also, adjustment of the RX EQ located at register offset 0x11 may help.

    Address 0xF6 thru 0xF7 report errors associated with DSI to DP video timing. Typically, errors are set in these registers when video timing programmed into DSI86 doesn’t match timing received on the DSI interface. It is important the DSI86’s video registers located from 0x20 thru 0x3A match video timing used by the DSI source. The DSI86 will derive the DP timings from values programmed into these registers.

    Thanks

    David

  • Hi David:

    I change another EDID from 1080P monitor, as list. and excute initial flow, from error register is all pass, but still no display.( it show no video stream)

    0 FF FF FF FF FF FF 0 10 AC 99 A0 4C 30 56 35
    10 1A 1 4 A5 30 1B 78 E2 EB F5 a6 56 51 9c 26
    10 50 54 a5 4b 0 71 4f 81 80 a9 c0 d1 c0 1 1
    1 1 1 1 1 1 2 3a 80 18 71 38 2d 40 58 2c
    45 0 dd 0c 11 0 0 1e 0 0 0 ff 0 32 30 43
    31 59 36 34 43 35 56 30 4c 0a 0 0 0 fc 0 44
    45 4c 4c 20 50 32 32 31 34 48 0a 20 0 0 0 fd
    0 38 4c 1e 53 11 0 0a 20 20 20 20 20 20 0 ef

    And this status confirm with SOC vendor,vendor answer that we need to moify driver to meet.

    So currently we are modifying dirver to try, thank you.

  • Hi,

    Ok, I will update for your update. Have you tried to enable the DSI86 color bar and does it work with this EDID? 

    Also, does the monitor support ASSR? The DSI86 by default supports ASSR. If the monitor does not support ASSR, then you will have to disable the DSI86 ASSR function as well. You can reference to the DSI86 programming spreadsheet 'Script_NoASSR' work tab.

    Thanks
    David