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DP83867CS: SGMII questions and Schematic check

Simon Appleby
Prodigy 10 points
Part Number: DP83867CS
Other Parts Discussed in Thread: TPS74701

Hi,

I am using a DP83867CS connected to an NXP LS1012a using SGMII 4-wire mode.

Initially I had difficulty with RX packets silently being dropped. I added the strapping on RX_CTRL as indicated on this forum post, which resolved this issue:
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/490569/c6678-dsp--dp83867-phy-sgmii-link-up-issue

After modifying the strapping, I now have no problem with the link and it would appear I am no longer seeing packet loss.

My questions are as follows:

For SGMII is it required for the local 25Mhz oscillator to be synchronous to the SGMII signals?
When I examine the PHY's 0x37 register it is always 0x40, Does this indicate other issues with the SGMII connection?

Do I need any other strapping not indicated in the data sheet for reliability or other recommendations?

Here is our schematic:


Thanks in advance for your attention

  • 0
    TI__Mastermind 19250 points

    Hi Simon,

    Thank you for reaching out to us.

    Is the SGMII Auto-negotiation enabled? You can read reg<0x14>[7] to check if the auto-negotiation is enabled.
    At what time instant are you reading Reg<0x37>? Can you please read it immediately after PHY link-up and before starting the data transfer?

    SGMII output signals (SOP, SON) are synchronous to the 25MHz clock. The input signals need not be synchronous to the 25MHz clock. DP83867 has CDR circuitry which takes care of phase and frequency offset.

    Let me take a detailed view of the schematic and get back to you by Tuesday (26-Apr).

    --
    Regards,
    Gokul.

  • 0 in reply to Gokul Koraganji
    TI__Mastermind 19250 points

    Hi Simon,

    Here is my feedback on the schematic.

    Power Supply Network:
    Please use the recommended power supply decoupling network specified in datasheet section 10 for all the supplies.
    For VDDIO, VDDA1P8 pins, the fanout of the LDO voltage can't be the same. There should be different lines of fanout from a point closer to the LDO output.
    Please check with the LDO team on the connections of LDO TPS74701

    Crystal:
    Please check with the crystal vendor, the optimum value of load caps and XO series resistor.

    MDI:
    Please share the schematic with the magnetic connection of differential lines.

    MDC/MDIO:
    Please add a pull-up resistor of 1.5k or 2.2k on MDIO pin

    --
    Regards,
    Gokul.