TFP401: ODCK Clock output doubts

Fabrizio Pizzolato

Part Number: TFP401

Hi all,

in my design, TFP401 is configured so that DFO input pin is Low; this means that ODCK clock runs continuously. When no video input is connected, I measure a frequency of about 1,5 MHz; the problem is that sometime, after a long usage, that frequency drops to about 500hZ. If logic is connected to this clock, like is my case, errors can occur in the elaboration. The question is: is this a known issue? What can cause it? Ho can I solve, other than using the internal oscillator for clocking logic? I think a redesign of the system is more elegant, I want however try to understand what is wrong with current implementation

Best regards

Fabrizio

over 3 years ago

0 David (ASIC) Liu over 3 years ago

TI__Guru**** 177646 points

Fabrizio

How are you controlling the /PDO pin? Driving the /PDO pin low would put all output pins, except CTL1 and SCDT, into a high-impedance state.

Thanks

David

0 Fabrizio Pizzolato over 3 years ago in reply to David (ASIC) Liu

Prodigy 10 points

Hi, the /PDO pin is left unconnected; we are relying on the internal pull up, as per datasheet, page 4 ("When /PDO is left unconnected, an internal pullup defaults the TFP401A to normal operation")

Fabrizio

0 David (ASIC) Liu over 3 years ago in reply to Fabrizio Pizzolato

TI__Guru**** 177646 points

Fabrizio

With the /PDO pin left unconnected and input is not connected, you will have a free running clock scenario and the TFP401 output state is not guaranteed.

But you can use the SCDT output, which indicates link-disabled or link-inactive, and tie it directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected. In this case, the output will then be high impedance.

Thanks

David

0 Fabrizio Pizzolato over 3 years ago in reply to David (ASIC) Liu

Prodigy 10 points

Thanks, you're confirming that the free running clock do not have an estabilished frequency, so even if it was not the original plan, I will not use it in the subsequent logic, thus avoiding the issue.

Best regards

Fabrizio

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TFP401: ODCK Clock output doubts