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TFP401: ODCK Clock output doubts

Part Number: TFP401

Hi all,

in my design, TFP401 is configured so that DFO input pin is Low; this means that ODCK clock runs continuously. When no video input is connected, I measure a frequency of about 1,5 MHz; the problem is that sometime, after a long usage, that frequency drops to about 500hZ. If logic is connected to this clock, like is my case, errors can occur in the elaboration. The question is: is this a known issue? What can cause it? Ho can I solve, other than using the internal oscillator for clocking logic? I think a redesign of the system is more elegant, I want however try to understand what is wrong with current implementation

Best regards

Fabrizio