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DS90UB954-Q1: Why 0x43 would mean less lock loss and when does AEQ increments EQ or SP

Mathieu Ghetti
Prodigy 30 points
Part Number: DS90UB954-Q1

Hi TI team,

I would like to ask 2 questions as below:

1)  Previously I received some advice from TI that increase register 0x43 (AEQ_ERR_THOLD) would result in less lock loss and I would like to understand why this is the case? Is this because every time the ERR_THOLD is met the EQ or SP is increments and during this incrementation a lock loss occurs or is it some other reason?

2) When the AEQ_ERR_THOLD is met when does the EQ or SP increment? Lets say my AEQ_ERR_THOLD is set to 1 and on the 4th byte of the image packet of 10bytes an error occurs, will the SP or EQ be incremented after the image packet is sent or will it increment on the 4th byte. If it is incremented of the 4th byte can this cause errors in the rest of the packet?

Thankyou very much.

  • 0
    TI__Guru 66840 points

    Hi Mathieu, 

    Mathieu Ghetti said:
    1)  Previously I received some advice from TI that increase register 0x43 (AEQ_ERR_THOLD) would result in less lock loss and I would like to understand why this is the case? Is this because every time the ERR_THOLD is met the EQ or SP is increments and during this incrementation a lock loss occurs or is it some other reason?

    Are you referring to lock loss/recovery transitions during AEQ specifically, or normal operating conditions? AEQ_ERR_THOLD should only apply to AEQ process.

    Mathieu Ghetti said:
    2) When the AEQ_ERR_THOLD is met when does the EQ or SP increment? Lets say my AEQ_ERR_THOLD is set to 1 and on the 4th byte of the image packet of 10bytes an error occurs, will the SP or EQ be incremented after the image packet is sent or will it increment on the 4th byte. If it is incremented of the 4th byte can this cause errors in the rest of the packet?

    This register/threshold is only for AEQ sequence during initial lock sequence. 

    Regards, 

    Logan

  • 0 in reply to Logan Cummins
    Prodigy 30 points

    Thanks logan.

    1) I am referring to lock loss during normal operating conditions. I was told that increasing 0x43 would result in less lock loss

    2) If that is the case that 0x43 AEQ_ERR_THOLD is only used during initial lock sequence. When does the system during normal operation decide to go to the next EQ position?

  • 0 in reply to Mathieu Ghetti
    TI__Guru 66840 points

    Hi Mathieu, 

    Let me clarify, AEQ is only iterated during initial lock OR after subsequent lock loss during normal operation (as a result of link margin issues, VDD/environmental event, etc).

    AEQ_ERR_THOLD does not improve the over-all margin of the link and will not result in less lock losses. 

    Increasing or lowering the AEQ_ERR_THOLD will only change the pass/fail threshold to decide to stay at current EQ or move to next. Technically, lowering this to lower thresholds might weed-out some marginal EQ settings (resulting in more temporary lock-losses during AEQ process), which might be marginally more stable after lock is achieved. Increasing AEQ_ERR_THOLD requires more errors during AEQ process to move to next AEQ, so will have potentially less AEQ related lock-loss cycles before settling on a valid AEQ setting. 

    All in all though, AEQ_ERR_THOLD doesn't really change the over-all margin of the link itself, and won't translate too much to link lock stability during normal operation.

    Regards, 

    Logan