Other Parts Discussed in Thread: TL16C750
Hello,
While testing out our design using the TL16C750E, we came into an odd behavior.
We are using the component in RS485 mode so /DTR is our TX_EN and /RX_EN signal for the transceiver connected after the component to connect to the RS485 signal.
Here is what we observed:
- At reset, the component sets /DTR high and TX high (as stated in the datasheet). Thus the RS485 output is high after the transceiver.
- After the reset phase, /DTR is kept high the TX output goes low. Thus the RS485 output is low after the transceiver.
- Once the component is configured in RS485, /DTR is still kept high and the TX output goes back high. Thus the RS485 output is high after the transceiver.
- After the transmission of a first byte, /DTR goes low, thus putting the RS485 output hi-Z.
I see two problems there:
- The toggling of TX high/low at the beginning could loose the receiver in front as it looks like a start bit.
- If the TL16C750 is not master of the bus, then there will be a collision until a first byte is transmitted by the component.
Is this behavior known/as expected ?
I have taken some oscilloscope screenshots below.
This first one shows a long recording, we see the component startup then a long delay before something happens (data exchange from TL16C750 to a CPU) which corresponds to us starting the CPU debugger to configure the part and start communicating.
A zoom of the startup:
A zoom of the behavior at TL16C750 configuration and before data is exchanged first:
A bigger zoom of the behavior after first exchange (bad resolution as we are working on a high time period on the oscilloscope):
Best regards,
Clément
