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DP83TD510E: RGMII Media Converter Problem

Cyrus Kelly
Prodigy 240 points
Part Number: DP83TD510E
Other Parts Discussed in Thread: DP83822I

Hello,

I am trying to make a 10BASE-T1L to 10BASE-T media converter circuit using the DP83TD510E and the DP83822I.  I built prototypes.  The RGMII is not working to pass data from the 822 to the 510.  The RGMII passes data fine from the 510 to the 822.  The traffic tester reports CRC and alignment errors.

The DP83TD510E has no timing diagrams for RGMII.  Looking at the timing diagrams for the DP83822I I am wondering if the problem is there is no shift on the 822 RX_CLK to 510 TX_CLK connection.  The datasheets for the 2 parts indicate

  • The DP83822I has no shift added to the RX_CLK, but there is a shift added to the TX_CLK.  
  • The DP83TD510E no shift is added to the RX_CLK, or the TX_CLK.  

I have no microcontroller on the board to send MDIO commands.  The PHYs are configured by straps.  Here are how the straps are configured.

DP83822I :

PIN   PIN #  Internal Set to DESCRIPTION
NAME PU/PD MODE
--------------------------------------------------------------------------------------------------------------------------
COL  29 PU 4 Internal PU - disables 100BASE-FX, set PHY addr to 00001.
RX_D0  30 PD 2 External 10K PU and 2.49K PD - sets 10BASE-Te, half/full duplex, and PHY addr to 00001.
RX_D1  31 PD 1 Internal PD - disables EEE, set PHY addr to 00001.
RX_D2  32 PD 1 Internal PD - disables Fast Link Drop, set PHY addr to 00001.
RX_D3  1 PD 1 Internal PD - sets 10BASE-Te, half/full duplex, and PHY addr to 00001.
LED_0  17 PU 4 Internal PU - sets 10BASE-Te, half/full duplex.
CRS  27 PU 1 External 1.96K PD - configure LED_0 as Link and Activity.
RX_ER  28 PU 3 External 1.96K PD, 6.2K PU - enables Auto-MDIX, enables RGMII.
RX_DV  26 PD 1 Internal PD - Set RGMII mode with 25MHz reference clock provided at XI pin.

DP83TD510E:

STRAP   PIN   PIN #  Internal DESCRIPTION
#   NAME PU/PD
--------------------------------------------------------------------------------------------------------------------------
1 RX_D3  13 PD Internal PD - sets PHY address to 0000.
2 RX_D2  14 PD Internal PD - sets pin 18 as CRS_DV.
3 RX_D1  15 PD Internal PD - sets PHY to RGMII mode.
4 RX_D0  16 PD Internal PD - sets PHY address to 0000.
5 RX_DV  18 PD Internal PD - sets Clockout/LED_1 pin as 25MHz clock output.
6 RE_ERR  20 PD Internal PD - sets PHY address to 0000.
7 LED_2  28 PD External PU - sets APL TX/RX voltage level to prefer 1 Vpp.
8 LED_0  29 PD External PU - sets PHY to RGMII mode.
9 GPIO1  32 PD Internal PD - sets PHY address to 0000.
10 GPIO2  8 NA Mandatory PD - sets Receiver with tapping at 50 Ω.

I'm not sure what the problem is for sure.  The delay is just a guess.  If you have any ideas on what might be wrong and how to figure out what it is and fix it I would love to hear them.

Thanks

  • 0
    TI__Mastermind 39855 points

    Hi Cyrus,

    I wanted to check how you were able to set a shift on TX_CLK for DP83822 as there is no strap settings that enable this; only register commands.

    As such, the only way to get communication to work is to get the shifts enabled for both TX_CLK and RX_CLK. This will either have to be done by implementing a microcontroller to adjust the register via SMI, or through a "hardware delay" by having longer traces.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 240 points

    Hello Gerome,

    My understanding from the DP83822 datasheet is that the TX_CLK shift is enabled by default:

    Based on this and the fact I have communications working in only one direction I am just guessing the TX_CLK is shifted. 

    I have not done any register commands (I can't) so both PHYs are set by straps only.  Should RGMII work for a media converter with a strap setup only?  I am sure hoping so.  Otherwise these boards I have are scrap.

    Excuse my ignorance, but if I do need to have a microcontroller to configure the PHYs, does it need to have a special interface or do you just connect to the MDIO and MDC with GPIO?

    Thanks,

    Cyrus

  • 0 in reply to Cyrus Kelly
    TI__Mastermind 39855 points

    Hi Cyrus,

    It appears that way unless accounted for in the layout. As long as the MCU can meet both device's SMI timing requirements, you may use GPIO pins requirements. A good reference guide is our DP83TD510E EVM, where we have a MSP430 device connecting to both PHYs.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 240 points

    Hello Gerome,

    OK, thanks.

    Here is another approach I am considering:  Could I put 2 inverters in the DP83822 RX_CLK output to delay it?  If this is a good approach, can you suggest a part or the characteristics to look for for it to work?  

    I looked at the DP83TD510E RGMII TIMING (10M) tables:

    If I interpret this correctly, I need a 40ns delay, correct?  If so, what is the maximum allowed delay?

    If 40ns is correct, then I would need 7m of clock trace to delay it enough - not practical!  I'm not even sure how many inverters I would need to pass the clock through to get a 40ns delay.

    Cyrus

  • 0 in reply to Cyrus Kelly
    TI__Mastermind 39855 points

    Hi Cyrus,

    Please allow me to bring this into discussion with the team. I expect feedback no later than Wednesday.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    TI__Mastermind 39855 points

    Hi Cyrus,

    Just checking, you mean 7m = 7 meters? I believe that since the RGMII speed is 10mbps, that would make the signaling 2.5MHz, or a period of 400ns. Assuming a duty cycle of 50% that means on time is 200ns. As long as the setup and hold time is not being violated, I don't see an issue with configuration. 

    As a suggestion, you can look at your board and scope out the MAC lines to see how the 510->822 path is working and compare that to the 822->510 path to get a reference on any adjustments you need to make on your board if needing to spin out a new board with longer traces.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 240 points

    Hello Gerome,

    Yes, 7m = 7 meters.  At 0.15m/ns propagation delay I would actually need 6m of extra trace length on the clock to get a 40ns delay.  That isn't practical.

    So, if the data is stable for 40+ ns before the clock edge and the data is stable for 40+ ns after the clock edge it will work (so a delay of anywhere from 40 to 160 ns), correct?  

    Looking at the MAC lines on the PCB will not help because the 822 adds its TX_CLK shift internally.

    Cyrus

  • 0 in reply to Cyrus Kelly
    TI__Mastermind 39855 points

    Hi Cyrus,

    Since this is the case, we would recommend putting a programmability feature into your design in order to talk to PHY via SMI. 

    Sincerely,

    Gerome