XIO2213B: some questions about XIO2213

Hi Kailyn,

I have received the question an I'm working on a response.  Sorry for the delay, please give me 24 more hours for this multi-part question.

Regards,

Nicholaus

1. About the REFCLK+/REFCLK-, if it could accept 100MHz LVDS input clock.  As the datasheet described, what is the common voltage of REFCLK?
I will follow-up with a second response regarding this question.

2.CPB input threshold voltage is 4.7V ~7.5V, but CPB connected 12V bus power of XIO2213EVM, so what is the maximum bus power ? 
The maximum bus power supported is defined by the PCIe specification is up to 75W depending on the type of slot that is designed. The CPS pin is typically used to detect cable power dropping below the threshold voltage, but if it is not being used it may be connected to Vssa as described in the datasheet. It seems like the bus that is providing power is determined by fuses on the EVM. The PCIe bus has a 0.5A fuse, so 0.5A*12V=6W. What is the concern regarding the maximum bus power?

3.LPS_L and LPS_P need short connection, but they also pull down to GND of XIO2213EVM, why they need pull down?
A pull down to GND is not required, but it is used in the EVM to place the PHY-section/LLC-section interface into low power state in which CTL and D outputs are held in logic 0 state and LREQ input is ignored. It is a similar case for the LKON pin to force the port into bilingual mode.

4. CTL0/CTL1/D[7:0] are float of XIO2213EVM, I wonder if they are float, do they affect the conversion between PCIE and 1394? CTL0/CTL1/D[7:0] are the control and data bus about PHY and LLC, so I am not sure if they could float directy? Like the EVM schematic, if they could float, what are their function of CTL0/CTL1/D[7:0] ?
These are able to float because of the situation described in question #3. The LPS-P input is considered inactive it remains low for more than the LPS_DISABLE time, which will put the PHY-section/LLC-section into a low-power state in which PCLK_P output is held inactive. This means the CTL and D outputs are held in a logic 0 state. The XIO2213B continues the necessary PHY repeater functions required for normal network operation, regardless of the state of the PHY-section/LLC-section interface.

Regards,

Nicholaus

1. About the REFCLK+/REFCLK-, if it could accept 100MHz LVDS input clock.  As the datasheet described, what is the common voltage of REFCLK?
   According to the PCIe specification, Vcross for a single-ended clock measurement is 250mV to 550mV.  This means that common mode should be around 400mV.  It is more common for HCSL clocks to be used as a PCIe reference clock for this reason.