XIO2213B: PCIe Differential Reference Clock Input

Hi Yu Lidong,

I see your questions and I'm working on a response.  Please give me some time to answer this multi-part question.

Regards,

Nicholaus

1Vid range:0.0675V~0.6V，is it right？
Yes, that is correct for a single-ended measurement.

2What is the Vicm range? Is the LVDS level OK?
I'm looking into this and will follow-up with a second response.

3The XIO2213B design has no internal 50-Ω-to-ground termination resistors. Both REFCLK inputs, at approximately 20 kΩ to ground, are high-impedance inputs.  Therefore, should I additionally add 50-Ω-to-ground termination resistors at these two pins?
I'm looking into this and will follow-up with a second response.

4The following figure shows a solution of the PCI-Express Reference Clock Inputs,is it ok ?
This is related to question #2.  I'm looking into this and will follow-up with a second response.

1What is the range of BUS_POWER that will not cause the voltage of the CPS exceed the XIO2213b's recommended input range?
BUS_POWER should monitor the cable power, so the maximum voltage input range should be defined by the 1394 specification used, around 12.8VDC nominal.

2Why add a pull-down resistor(R15) at LPS?
A pull down to GND is not required, but it is used in the EVM to place the PHY-section/LLC-section interface into low power state in which CTL and D outputs are held in logic 0 state and LREQ input is ignored.  It is a similar case for the LKON pin to force the port into bilingual mode.

3I think XIO2213 contains LLC and PHY, so if the pins(CTL0/CTL1/D[7:0]) are not connected, will it not cause the PCI Express to 1394b translation to fail?

If the pins (CTL0/CTL1/D[7:0]) do not need to be connected and the XIO2213b is capable of PCI Express to 1394b conversion, then why does the XIO2213b pin out these pins (CTL0/CTL1/D[7:0]) and what is their usage scenario?

The reason I have this doubt is that the pins such as CLK_P, PCLK_L, LCLK_P, LCLK_L, etc. are defined in the datasheet as clock inputs and outputs between 1394 link layer and physical layer, etc. After the XIO2213b pins them out, the user needs to do the connection externally by himself;

Similarly, I just assume that the pins(CTL0/CTL1/D[7:0]), which also act as the control and data bus signals of 1394 link layer and physical layer, must also be processed to accomplish the PCI Express to 1394b translation.

These are able to float because of the situation described in question #2.  The LPS-P input is considered inactive it remains low for more than the LPS_DISABLE time, which will put the PHY-section/LLC-section into a low-power state in which PCLK_P output is held inactive.  This means the CTL and D outputs are held in a logic 0 state.  The XIO2213B continues the necessary PHY repeater functions required for normal network operation, regardless of the state of the PHY-section/LLC-section interface.

Regards,

Nicholaus

1. About the REFCLK+/REFCLK-, if it could accept 100MHz LVDS input clock.  As the datasheet described, what is the common voltage of REFCLK?
   According to the PCIe specification, Vcross for a single-ended clock measurement is 250mV to 550mV.  This means that common mode should be around 400mV.  It is more common for HCSL clocks to be used as a PCIe reference clock for this reason.
2. The XIO2213B design has no internal 50-Ω-to-ground termination resistors. Both REFCLK inputs, at approximately 20 kΩ to ground, are high-impedance inputs.  Therefore, should I additionally add 50-Ω-to-ground termination resistors at these two pins?
   Yes, according to the PCIe specification the clock source usually provides these 50ohm terminations.

Regards,

Nicholaus

Hi Nicholaus, thank you for your answer.

1. As you said, according to PCIE standard, REFCLK+/REFCLK- should be connected to HSCL level. Therefore, I'm going to modify my PCIE connection scheme as shown below，is it ok?

2. I have understood how the pull-down resistor at the LPS pin on XIO2213B EVM works now. However, when I set the CPS of Host Controller Control Register to 1, the PHY-section/LLC-section is active . When PHY-section/LLC-section is active and the pins (CTL0/CTL1/D[7:0]) are left open, is the XIO2213b capable of PCI Express to 1394b translation?

I see the following connection scheme in the TSB81BA3/TSB82AA2 datasheet.

In the figure above, the the pins (CTL0/CTL1/D[7:0]) of the LLC(TSB82AA2)and PHY(TSB81BA3) should be connected to enable 1394 to PCI translation.

Then, for the XIO2213b, do the pins(CTL0/CTL1/D[7:0]) not play any role in the XIO2213's implementation of PCIE to 1394 conversion?If they can left open when PHY/LCC is active or inactive，why are these pins pinned out and when do I need to use them?

1. This looks OK based on the block diagram. 

2. The datasheet suggests that the EVM would have the PHY active, but the LLC would not be active due to it not using the CTL and D pins.  I following-up internally to understand why these pins are not routed to the connectors in the EVM and when they need to be used.

Regards,

Nicholaus