SN65DSI86EVM: When using external DSI clock, The test pattern cannot be displayed and Semi_Auto Link Training fails.

Hi David,

Thank you for your reply,

Actually, the customer uses 500MHz for DSIA CLK.

This frequency is not usable frequency.

I'll share this information with the customer and change to recommended frequency.

When they have an additional question, I consult you again.

I appreciate your great help and cooperation.

Best regards,

Shinichi

Shinichi-san

For DSI86 programming guide, please refer to this app note, https://www.ti.com/lit/an/slla425/slla425.pdf.

For the DSI86 register programming value, you can use the spreadsheet in this e2e guide, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945404/faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers.

Thanks

David 

Hi David,

Thank you for your reply.

I'll share the documents you send with the customer.

I'd like to confirm.

You mentioned "When using the REFCLK as the clock source, any DSI Clock frequency is supported".

Actually, the customer'd like to use 500MHz of DSI CLK.

In this case,  if REFCLK is used for clock source, SN65DSI86 can support 500MHz of DSICLK.

I appreciate your great help and cooperation.

Best regards,

Shinichi

Shinichi-san

This is correct, please also see my initial response and the app note on how to calculate the DIS CLK frequency.

Thanks

David

Hi David,

Thank you for your reply.

I understand it can support 500MHz DSI clock when REFCLK is used for clock source.

I appreciate your great help and cooperation.

Best regards,

Shinichi

Hi David,

Could you please let me know in detail.

REFCLK is supported 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz.

Can all of these frequency support 500MHz.

I appreciate your great help and cooperation.

Best regards,

Shinichi

Hi David,

Thank you for your reply.

I'll share this with the customer.

I appreciate your great help and cooperation.

Best regards,

Shinichi

Hi David,

The customer has additional questions.

Could you please let us know the advise.

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Q1: What is the role of REFCLK (for example, 27Mhz)?
Generally, from the DSI source on the user side, the data lane and the clock lane are input to the IC, and the data rate is determined by the clock lane.

I think the data rate should be determined with or without REFCLK on the IC side.

Please tell me about the relationship between REFCLK and DSICLK.

Q2: Related to Q1 above, I used to think that when using the DSI clock lane DSIACLK (DACP / N) at 500Mhz, the clock on the REFCLK pin (27Mhz) had to be stopped.

This understanding is wrong and you need to use REFCLK, right?

Is it correct to understand that REFCLK is only used for the PLL lock of DSIACLK, DSI transfer is performed in synchronization with DSIACLK, and

DSIACLK can be arbitrary up to 750Mhz (max)?

Q3: In our evaluation, when the REFCLK pin = 27Mhz and the DSI clock lane (DSIACLK) = 500Mhz, the Semi_Auto_Link test sometimes succeeded or failed.
After changing to DSIACLK = 485Mhz (because 486Mhz cannot be generated), the Semi_Auto_Link test is almost successful.

What could be the reason for this?

I don't think the DSIACK frequency affects the Semi_Auto_Link test, but the results do.

Q4: When the REFCLK pin = clock is stopped, the Semi_Auto_Link test fails even if the DSI clock lane (DSIACLK) = 485Mhz (0xF8 register: LT_Fail occurs).

Will the Semi_Auto_Link test fail without REFCLK?

Q5: Our environment is REFCLK pin = 27Mhz, DSIACLK = 485Mhz (changed from 500Mhz), but after the Semi-Auto-Link test succeeds, the DSI transfer from our DSI source to the IC fails.

The cause may be that the Protocol processor inside the IC has detected CHA_SOT_BIT_ERR (0xF0 register), CHA_DATATYPE_ERR,

CHACHECKSUM_ERR, CHA_UNC_ECC_ERR, etc. (0xF1 register) from the result of the CSR bit field.

We would appreciate it if you could let us know how to deal with it.

I appreciate your great help and cooperation.

Best regards,

Shinichi

Shinichi-san

Please tell me about the relationship between REFCLK and DSICLK.

*** See this table below

To properly sample high-speed data received on the DSI interface, the DSIx6 implements a hardware mechanism, known as DSI_CLK_RANGE Estimator, to determine the DSI clock frequency. This hardware mechanism uses the REFCLK as a reference for calculating the DSI clock frequency.

So have they used the spreadsheet I sent to generate the DSI86 register programming value? And if they did, can you please share the spreadsheet?

In the DSI86 datasheet, the table below showed the DSI Data Type supported by the DSI86, are they using the right data type when sending the DSI data?

Thanks

David

Hi David,

Thank you for your reply.

I'll share your advise you send with the customer.

When I obtain the feedback from the customer, I'll send to you.

I appreciate your great help and cooperation.

Best regards,

Shinichi

Hi David,

I sent excel file and application note to the customer.

They're confirming. When I could obtain the result, I'll share with you.

By the way, they have an additional question about  the excel file.

Could you please advise.

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Looking at the script data "Script_NoASSR" in the Excel sheet, this is for outputting the color bar.

(could you please refer to near the end'===== Color Bar Enable ======),

Even we have succeeded so far.

Could you please let us know the code to successfully transfer the DSI data from the DSI source side to the monitor.

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I appreciate your great help and cooperation.

Best regards,

Shinichi

Hi David,

Thank you for your reply.

The customer are trying to solve themselves by comparing video format from the DSI with test pattern.

If they have an additional question, I consult you again.

I appreciate your great help and cooperation.

Best regards,

Shinichi