DP83869HM: SGMII GigE Connection

Hi Daniel,

What is the link partner and how is it configured? This is what will determine the auto-negotiation selection. 

Can you provide a register dump of the DP83869 so we can double check the register settings?

Thanks,

David

The link partner is a Gigabit switch which is connected to a windows PC. We have a previous version of this custom PCB which is able to connect to this PC at 1000M though the switch. I have attached the register dump at the end of this post. I have also attached the schematic page for this PHY and the gerber for the connection between the PHY and the jack. A few things of note:

1) The termination resistor network on the MDI lines was an artifact of the previous board. I believe these should be removed, but I am unsure if this would cause 1000M not to work properly? 

2) There are unmatched vias on two of the MDI lines which cause ~1pF of capacitance difference between the lines of the diff pair, but I don't believe that delay would cause this to not work? 

3) I have the MDI diff pairs length matched, but the 4 channels are not length matched to each other.

4) We do not have any circuit protection in place since this board is connected to a switch and not the outside world. 

I am in the process of going through the DP83867 Troubleshooting Guide and will update this post with any additional information if found.

Thanks,

Dan

Ethernet Page.pdf

BMCR 4416
BMSR 31081
PHYIDR1 8192
PHYIDR2 41201
ANAR 481
ALNPAR 50657
ANER 111
ANNPTR 8193
ANLNPTR 30721
GEN_CFG1 2816
GEN_STATUS1 0
REGCR 16415
ADDAR 4416
ONEKSCR 61440
PHY_CONTROL 20552
PHY_STATUS 31746
INTERRUPT_MASK 0
INTERRUPT_STATUS 23874
GEN_CFG2 10695
RX_ERR_CNT 0
BIST_CONTROL 0
GEN_STATUS2 64
LEDS_CFG1 24912
LEDS_CFG2 17476
LEDS_CFG3 2
GEN_CFG4 18
GEN_CTRL 0
ANALOG_TEST_CTRL 0
GEN_CFG_ENH_AMIX 0
GEN_CFG_FLD 0
GEN_CFG_FLD_THR 0
GEN_CFG3 0
RGMII_CTRL 80
RGMII_CTRL2 0
SGMII_AUTO_NEG_STATUS 3
PRBS_TX_CHK_CTRL 0
PRBS_TX_CHK_BYTE_COUNT 0
G_100BT_REG0 1952
SERDES_SYNC_STS 278
STRAP_STS 3072
ANA_RGMII_DLL_CTRL 119
RXF_CFG 4096
RXF_STATUS 0
IO_MUX_CFG 3088
TDR_GEN_CFG1 1874
TDR_GEN_CFG2 51280
TDR_SEG_DURATION1 21286
TDR_SEG_DURATION2 40990
TDR_GEN_CFG3 59766
TDR_GEN_CFG4 6607
TDR_PEAKS_LOC_A_0_1 0
TDR_PEAKS_LOC_A_2_3 0
TDR_PEAKS_LOC_A_4_B_0 0
TDR_PEAKS_LOC_B_1_2 0
TDR_PEAKS_LOC_B_3_4 0
TDR_PEAKS_LOC_C_0_1 0
TDR_PEAKS_LOC_C_2_3 0
TDR_PEAKS_LOC_C_4_D_0 0
TDR_PEAKS_LOC_D_1_2 0
TDR_PEAKS_LOC_D_3_4 0
TDR_GEN_STATUS 0
TDR_PEAKS_SIGN_A_B 0
TDR_PEAKS_SIGN_C_D 0
OP_MODE_DECODE 70
GPIO_MUX_CTRL 16762
FX_CTRL 4416
FX_STS 24937
FX_PHYID1 8192
FX_PHYID2 41201
FX_ANADV 32
FX_LPABL 16385
FX_ANEXP 3
FX_LOCNP 8193
FX_LPNP 0
FX_INT_EN 511
FX_INT_STS 17

Hi Daniel,

Thank you for the information. The notes you listed may definitely affect the signal quality, but it is hard to quantify. First I would like to confirm if it is an auto-negotiation issue, or a board design/ signal integrity issue like you suspect.

Can you try taking two of the DP83869 boards and linking them together? If it still comes up in 100Mbps, try disabling auto-negotiation on both sides and forcing the 1000Mbps operation. What happens then?

Can you also tell me which, if any, register settings you are changing from default before trying the link?

Let me know the answers to these and then I can do a more in depth review of schematic and layout if necessary.

Please also give us a little more background on the previous functional board vs this new nonfunctional one. What were all the changes made?

Thanks,

David

I will work through your suggestion about connecting the two boards directly. I also just received in the development board for this part if there is any debugging activities I can do using that. In the meantime here are answers to your other questions.

1) Can you also tell me which, if any, register settings you are changing from default before trying the link?

The registers are configured based on section 9.4.8.6 of the data sheet. Register 0x01DF is set to reset values except for bits 2-0 which are set to 0x6 for SGMII to Copper. 

2) Please also give us a little more background on the previous functional board vs this new nonfunctional one. What were all the changes made?

This is a complete redesign of the board, which includes a new ethernet jack, magnetics, PHY, and FPGA. The previous PHY was a Marvell 88E1111, which was configured to interfaced with the FPGA through RGMII, the device was setup for AN advertising 10/100/1000Mb. The link partner has remained the same in both systems. 

Thanks,

Daniel 

Hi Daniel,

Thank you for the additional information. Do let me know what the results of the two board test are. 

Thanks,

David

David,

Here are the register readings with two boards connected to each other. The PHY_STATUS register indicates that the speed in 1000Mb following AN. I also repeated this test connecting with the dev board, which also indicated that the connection speed was 1000Mb following AN. 

Thank you,

Daniel 

BMCR 4416
BMSR 31085
PHYIDR1 8192
PHYIDR2 41201
ANAR 481
ALNPAR 49633
ANER 111
ANNPTR 8193
ANLNPTR 18432
GEN_CFG1 2816
GEN_STATUS1 15360
REGCR 16415
ADDAR 4416
ONEKSCR 61440
PHY_CONTROL 20552
PHY_STATUS 44802
INTERRUPT_MASK 0
INTERRUPT_STATUS 7488
GEN_CFG2 10695
RX_ERR_CNT 0
BIST_CONTROL 0
GEN_STATUS2 64
LEDS_CFG1 24912
LEDS_CFG2 17476
LEDS_CFG3 2
GEN_CFG4 18
GEN_CTRL 0
ANALOG_TEST_CTRL 0
GEN_CFG_ENH_AMIX 0
GEN_CFG_FLD 0
GEN_CFG_FLD_THR 0
GEN_CFG3 0
RGMII_CTRL 80
RGMII_CTRL2 0
SGMII_AUTO_NEG_STATUS 3
PRBS_TX_CHK_CTRL 0
PRBS_TX_CHK_BYTE_COUNT 0
G_100BT_REG0 1952
SERDES_SYNC_STS 326
STRAP_STS 3072
ANA_RGMII_DLL_CTRL 119
RXF_CFG 4096
RXF_STATUS 0
IO_MUX_CFG 3084
TDR_GEN_CFG1 1874
TDR_GEN_CFG2 51280
TDR_SEG_DURATION1 21286
TDR_SEG_DURATION2 40990
TDR_GEN_CFG3 59766
TDR_GEN_CFG4 6607
TDR_PEAKS_LOC_A_0_1 0
TDR_PEAKS_LOC_A_2_3 0
TDR_PEAKS_LOC_A_4_B_0 0
TDR_PEAKS_LOC_B_1_2 0
TDR_PEAKS_LOC_B_3_4 0
TDR_PEAKS_LOC_C_0_1 0
TDR_PEAKS_LOC_C_2_3 0
TDR_PEAKS_LOC_C_4_D_0 0
TDR_PEAKS_LOC_D_1_2 0
TDR_PEAKS_LOC_D_3_4 0
TDR_GEN_STATUS 0
TDR_PEAKS_SIGN_A_B 0
TDR_PEAKS_SIGN_C_D 0
OP_MODE_DECODE 70
GPIO_MUX_CTRL 16762
FX_CTRL 4416
FX_STS 24937
FX_PHYID1 8192
FX_PHYID2 41201
FX_ANADV 32
FX_LPABL 16385
FX_ANEXP 3
FX_LOCNP 8193
FX_LPNP 0
FX_INT_EN 511
FX_INT_STS 17

Hi Daniel,

This seems like an auto-negotiation issue then. Was the first register dump sent when the board was connected to the switch? I see the GEN_STATUS1 register shows the link partner does not support 1000Base-T. 

Also just checking, what do you mean by "development board". Is this our DP83869EVM?

Thanks,

David

David,

The first register dump was when the board connected to the switch. Here are couple of data points which made me believe it wasn't the link partner: 

1. The register dump I have attached to this post is from the same system setup (custom PCB to switch). It was taken after AN completed and indicates the link partner is capable of 1000Base-T Full Duplex and the PHY_STATUS register indicates the selected speed is 1000Mb. The first register dump is from after a connection was made and data was being transmitted.
2. I am able to connect to this link partner with the older revision of this board at 1000Mb.
3. Enhanced Speed Optimization is enabled (bit 8 of the GEN_CFG2) so I believed the 1G link is failing and this is why the speed is being lowered. Not sure if this would explain why the link partner abilities in the GEN_STATUS1 register changes following AN? 

Thank you,

Daniel  

Register Dump after AN, before data is transmitting 

BMCR 4416
BMSR 31081
PHYIDR1 8192
PHYIDR2 41201
ANAR 481
ALNPAR 50657
ANER 111
ANNPTR 8193
ANLNPTR 22534
GEN_CFG1 2816
GEN_STATUS1 10240
REGCR 16415
ADDAR 4416
ONEKSCR 61440
PHY_CONTROL 20552
PHY_STATUS 47874
INTERRUPT_MASK 0
INTERRUPT_STATUS 23874
GEN_CFG2 10695
RX_ERR_CNT 0
BIST_CONTROL 0
GEN_STATUS2 64
LEDS_CFG1 24912
LEDS_CFG2 17476
LEDS_CFG3 2
GEN_CFG4 18
GEN_CTRL 0
ANALOG_TEST_CTRL 0
GEN_CFG_ENH_AMIX 0
GEN_CFG_FLD 0
GEN_CFG_FLD_THR 0
GEN_CFG3 0
RGMII_CTRL 80
RGMII_CTRL2 0
SGMII_AUTO_NEG_STATUS 3
PRBS_TX_CHK_CTRL 0
PRBS_TX_CHK_BYTE_COUNT 0
G_100BT_REG0 1952
SERDES_SYNC_STS 294
STRAP_STS 3072
ANA_RGMII_DLL_CTRL 119
RXF_CFG 4096
RXF_STATUS 0
IO_MUX_CFG 3088
TDR_GEN_CFG1 1874
TDR_GEN_CFG2 51280
TDR_SEG_DURATION1 21286
TDR_SEG_DURATION2 40990
TDR_GEN_CFG3 59766
TDR_GEN_CFG4 6607
TDR_PEAKS_LOC_A_0_1 0
TDR_PEAKS_LOC_A_2_3 0
TDR_PEAKS_LOC_A_4_B_0 0
TDR_PEAKS_LOC_B_1_2 0
TDR_PEAKS_LOC_B_3_4 0
TDR_PEAKS_LOC_C_0_1 0
TDR_PEAKS_LOC_C_2_3 0
TDR_PEAKS_LOC_C_4_D_0 0
TDR_PEAKS_LOC_D_1_2 0
TDR_PEAKS_LOC_D_3_4 0
TDR_GEN_STATUS 0
TDR_PEAKS_SIGN_A_B 0
TDR_PEAKS_SIGN_C_D 0
OP_MODE_DECODE 70
GPIO_MUX_CTRL 16762
FX_CTRL 4416
FX_STS 24937
FX_PHYID1 8192
FX_PHYID2 41201
FX_ANADV 32
FX_LPABL 16385
FX_ANEXP 3
FX_LOCNP 8193
FX_LPNP 0
FX_INT_EN 511
FX_INT_STS 49

Sorry, I realized I didn't answer your second question. Yes the development board I am referring to is the DP83869EVM.

-Daniel 

Hi Daniel, 

What do you mean by "custom PCB" in your latest post? 

Here are a few more experiments I would like to try:

1. Try disabling the speed optimization bit and see what  the behavior is. If it does nothing, restore to default. 

2. Connect your custom board with dp83869 to any other link partners you have available. Is it failing with all of them?

3. Disable auto-negotiation and force 1000Mbps operation on the custom board using the BMCR register. Force 1000Mbps operation on the switch side as well. 

4. Connect our 869EVM to your switch.

Let me know the results. Also, is it possible to send any future register dumps in Hex format? 

Thanks,

David

David,

The custom PCB is the custom board with the dp83869 part on it, sorry for the confusion.

1. The behavior remained the same. AN passed and 1000Mb selected but fails to connect and transmit data. We see a handful of packets sent over and then the connection drops. I have attached that register dump.

2. The custom board fails to connect to any link partner we have tried at 1000Mb (switch / direct to  windows PC / USB to ethernet adapter / panel PC).

3. We saw no traffic with this configuration. We are going to continue looking into this and try other speeds to confirm our manual configuration is being implemented properly.

4. I have attached a register dump from the 869EVM connected to the switch.

Thank you,

Daniel

Register 0000 is: 2100

Register 0001 is: 794D

Register 0002 is: 2000

Register 0003 is: A0F1

Register 0004 is: 01E1

Register 0005 is: 0000

Register 0006 is: 0064

Register 0007 is: 2001

Register 0008 is: 0000

Register 0009 is: 0300

Register 000a is: 4000

Register 0010 is: 5008

Register 0011 is: 6C02

Register 0012 is: 0000

Register 0013 is: 0480

Register 0014 is: 29C7

Register 0015 is: 0000

Register 0016 is: F008

Register 0017 is: 0A40

Register 001e is: 0012

Register 001f is: 0000

Register 0031 is: 10B1

Register 0037 is: 0000

Register 006e is: 1000

Register 01df is: 0000

Register Dump - No Speed Optimization 

BMCR 0x1140
BMSR 0x796d
PHYIDR1 0x2000
PHYIDR2 0xa0f1
ANAR 0x1e1
ALNPAR 0xcde1
ANER 0x6f
ANNPTR 0x2001
ANLNPTR 0x4006
GEN_CFG1 0xb00
GEN_STATUS1 0x7800
REGCR 0x401f
ADDAR 0x1140
ONEKSCR 0xf000
PHY_CONTROL 0x5048
PHY_STATUS 0xaf02
INTERRUPT_MASK 0x0
INTERRUPT_STATUS 0x1c42
GEN_CFG2 0x28c7
RX_ERR_CNT 0x0
BIST_CONTROL 0x0
GEN_STATUS2 0x40
LEDS_CFG1 0x6150
LEDS_CFG2 0x4444
LEDS_CFG3 0x2
GEN_CFG4 0x12
GEN_CTRL 0x0
ANALOG_TEST_CTRL 0x0
GEN_CFG_ENH_AMIX 0x0
GEN_CFG_FLD 0x0
GEN_CFG_FLD_THR 0x0
GEN_CFG3 0x0
RGMII_CTRL 0x50
RGMII_CTRL2 0x0
SGMII_AUTO_NEG_STATUS 0x3
PRBS_TX_CHK_CTRL 0x0
PRBS_TX_CHK_BYTE_COUNT 0x0
G_100BT_REG0 0x7a0
SERDES_SYNC_STS 0x106
STRAP_STS 0xc00
ANA_RGMII_DLL_CTRL 0x77
RXF_CFG 0x1000
RXF_STATUS 0x0
IO_MUX_CFG 0xc0c
TDR_GEN_CFG1 0x752
TDR_GEN_CFG2 0xc850
TDR_SEG_DURATION1 0x5326
TDR_SEG_DURATION2 0xa01e
TDR_GEN_CFG3 0xe976
TDR_GEN_CFG4 0x19cf
TDR_PEAKS_LOC_A_0_1 0x0
TDR_PEAKS_LOC_A_2_3 0x0
TDR_PEAKS_LOC_A_4_B_0 0x0
TDR_PEAKS_LOC_B_1_2 0x0
TDR_PEAKS_LOC_B_3_4 0x0
TDR_PEAKS_LOC_C_0_1 0x0
TDR_PEAKS_LOC_C_2_3 0x0
TDR_PEAKS_LOC_C_4_D_0 0x0
TDR_PEAKS_LOC_D_1_2 0x0
TDR_PEAKS_LOC_D_3_4 0x0
TDR_GEN_STATUS 0x0
TDR_PEAKS_SIGN_A_B 0x0
TDR_PEAKS_SIGN_C_D 0x0
OP_MODE_DECODE 0x46
GPIO_MUX_CTRL 0x417a
FX_CTRL 0x1140
FX_STS 0x6169
FX_PHYID1 0x2000
FX_PHYID2 0xa0f1
FX_ANADV 0x20
FX_LPABL 0x4001
FX_ANEXP 0x3
FX_LOCNP 0x2001
FX_LPNP 0x0
FX_INT_EN 0x1ff
FX_INT_STS 0x11

Hi Daniel,

I may have misunderstood the problem. So to clarify,  I see the custom PCB comes up in 1000Mbps, shows link status good, shows auto-negotiation complete, as shown by the PHY_STATUS register in your latest dump. And then after some time, it drops to 100Mbps? How long does it take to drop?

"AN passed and 1000Mb selected but fails to connect and transmit data. We see a handful of packets sent over and then the connection drops"

How are you judging the PHY is failing to connect and transmit data? By connection drops, do you mean it drops to 100Mbps, or link is dropped? Do you see traffic after the PHY drops to 100Mbps?

I will review your schematic and get back to you with any comments next week.

Thanks,

David

David, 

How are you judging the PHY is failing to connect and transmit data? By connection drops, do you mean it drops to 100Mbps, or link is dropped? Do you see traffic after the PHY drops to 100Mbps?

We are using WireShark to monitor the ethernet traffic. Yes, I see traffic continuously after the PHY drops to 100Mbps.

So to clarify,  I see the custom PCB comes up in 1000Mbps, shows link status good, shows auto-negotiation complete, as shown by the PHY_STATUS register in your latest dump. And then after some time, it drops to 100Mbps? How long does it take to drop?

Yes exactly. I believe what is happening is it attempts to send messages at 1000Mbps and then drops to 100Mbps due to the speed optimization. When speed optimization was off I could see 4-6 packets sent across before the link was dropped.

Thank you,

Daniel 

Hi Daniel, 

Understood. This is likely a signal integrity issue then. 

The register dump of the 869EVM to Switch shows auto-negotiation is turned off. If you turn auto-negotiation on, do you get traffic in 1000Mbps?

Will provide comments on the schematic next week.

Thanks,

David 

Hi Daniel,

Here are my comments on the schematic:

1. C58, C64, C72, C78 should be 10nf instead of 10uF

2. Ensure the crystal specs meet the requirements listed in section 10.2.1.2.1.1 of the datasheet

3. MDC pin should not have a pullup resistor

4. The DP83869 has integrated MDI termination resistors, so R37-R44 and C90-C93 are not recommended. Is there a reason this "Protection" section has been added?

5. Recommend adding option to isolate MDI connector ground to digital ground, as shown in the DP83869EVM schematic. 

Thanks,

David

David,

Thank you for the feedback, I will have these updated on the next revision of the board. The "Protection" was an artifact of the previous version of the board which used a different PHY.

One data point is that I can see communication (at 100Mb) through wireshark with these resistors in place and once I remove them I am no longer able to get any communication even at 100Mb. I am unsure at this point why that would be the case, any thoughts? 

Thank you,

Daniel 

Hi Daniel,

Thank you for the data point. I am unsure about this specific issue, but it sounds like there are enough artifacts of the previous board that are causing the issue you are seeing. 

Can you confirm that the DP83869EVM is operating correctly? If you turn auto-negotiation on, does it link up in 1000Mbps and produce traffic?

Thanks,

David

Hi David,

The DP83869EVM links up at 1000Mbps but I do not see any traffic. The traffic I referring to is TCP packets which are generated by a MAC layer, which I do not believe the eval board is capable of correct? I would have to connect additional hardware to the eval board in order to see traffic unless my understanding is incorrect?

Thank you,

Daniel 

Hi Daniel,

You are correct. Since there is no MAC on the EVM, you would not see TCP packets. However, since you have confirmed the EVM links up and stays in 1000Mbps, I think it is safe to say the issue here is with the schematic and/or layout of your custom board. 

Please update the board incorporating the comments I have listed above, as well as the principles described in section 12 of the datasheet and the Ethernet PHY PCB Design Layout Checklist. Use our EVM schematic as a reference as well.

Let me know if you have additional questions. 

Thanks,

David