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Original question:

SN65HVD09: Channel to Channel Skew

SN65HVD09: Input Capacitance

Nirmal Bommu
Prodigy 60 points
Part Number: SN65HVD09

In my design we were connected every input to one net. and i am passing 1PPS Signal with Rise time of 12ns and ON time as 800uS. In datasheet they didn't mentioned the input capacitance.

My doubt is that due to input capacitance of every connected channel will affect the Rise time of that signal?

  • 0
    TI__Guru 52172 points

    Hi Nirmal,

    You are correct attaching every input in parallel will increase the capacitive loading on the input signal. Its not a spec we typically use so we don't have that data on this part. The input capacitance is probably on the  order of 10's of pF since there are multiple logic connections each A input. Most logic input capacitances for logic circuits run between 3pF to 6pF on average input capacitance. The rise time is also related to the output impedance and capacitance of the PPS signal generator. 

    Please let me know if you have any other questions!

    Best,

    Parker Dodson