TL16C752D: cycle delay

Kurumi Hasegawa

Part Number: TL16C752D

Hi team,

I’ve got questions on the definition of the cycle delay.

On the datasheet, the Figure 1 and Figure 2 shows General Write/Read Timing diagram.

For writing, assuming the CS and IOW widths do not change but are repeated like the below image, how should I define t15d? Which one of the red arrows is correct (CS or IOW/R)?

For reading, assuming the CS and IOW widths do not change but are repeated like the below image, how should I define t9d? Which one of the red arrows is correct (CS or IOW/R)?

Best regards,

Kurumi

over 3 years ago

+1 Eric Schott1 over 3 years ago

TI__Guru 53575 points

Hi Kurumi,

The delay times defined here show the minimum delay required where the IOR or IOW signal need to be high before the next transaction begins. This is shown in Figure 1 and Figure 2 as the time between a rising edge of IOR/IOW and the following falling edge on the same signal. This requirement is independent of the address or chip select timings of the transaction.

Let me know if you have any more questions.

Regards,
Eric Schott

0 Kurumi Hasegawa over 3 years ago in reply to Eric Schott1

TI__Expert 7931 points

Hi Eric,

Understood, thank you!

Best regards,

Kurumi

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TL16C752D: cycle delay