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DP83848I: ISSUE: PHY freezes on power up

Dor Oliel
Prodigy 20 points
Part Number: DP83848I
Other Parts Discussed in Thread: DP83848VYB

Hello,

Every couple hundred of power ups the PHY freezes. the PHY receives the 25MHz clock but not returning anyting on the rx_clk or tx_clk.

when we do a rst to the PHY (without reseting any other componnent) the PHY unfreezes. the MDIO is working so hardware or software reset both succeed in unfreezing the PHY.

the 3.3V was monitored through startup there is no overshoot and the startup time is ~1ms.

RXD[0] was also monitored during reset from powerup and the line was stable.

Is the issue familiar?

Is conducting software reset after every powerup enough to ensure this issue will not occur on startup or in steady state operation?

same test was made on DP83848VYB and the issue did not appear with this product. since the product is with different footprint I cannot switch to use with it instead.

 Register state of the PHY in normal operation and in failed state:

normal fail
0x00 0x3100 0x3100
0x01 0x7849 0x7849
0x02 0x2000 0x2000
0x03 0x5C90 0x5C90
0x04 0x01E1 0x01E1
0x05 0x0000 0x0000
0x06 0x0007 0x0004
0x07 0x2001 0x2001
0x08 0x0000 0x0000
0x09 0x0000 0x0000
0x0A 0x0000 0x0000
0x0B 0x0000 0x0000
0x0C 0x0000 0x0000
0x0D 0x0000 0x0000
0x0E 0x0000 0x0000
0x0F 0x0000 0x0000
0x10 0x2800 0x4000
0x11 0x0000 0x0000
0x12 0x2E00 0x0000
0x13 0x0000 0x0000
0x14 0x00FF 0x0000
0x15 0x0015 0x0000
0x16 0x0100 0x0100
0x17 0x0001 0x0001
0x18 0x0000 0x0000
0x19 0x8021 0x8021
0x1A 0x0804 0x0804
0x1B 0x0000 0x0000
0x1C 0x0000 0x0000
0x1D 0x6011 0x6011
0x1E 0x003F 0x023D
0x1F 0x0000 0x0000

Thanks,

Dor

  • 0
    TI__Mastermind 25955 points

    Hi Dor,

    I have some questions for the further debug:

    • Could you shared the register status after reset?
    • Did you provide the 25MHz through crystal?
    • Could you shared the schematics
    • Could you try to connect a link partner during fail state? Because I saw both normal state and fail state the PHY is not linking up.

    --

    Regards,
    Hillman Lin

  • 0 in reply to Hillman Lin
    Prodigy 20 points

    Hi,

    The registers that presented above, are read right after reset.

    25MHz where supplied from MCO of STM32F107.

    the link partner exist in the fail state and in the normal state. after reading the registers the MCU is communicating through PHY for the normal state and in the fail state there is no communication except for the LED_SPEED that is on (pulled down).

    rx_clk and tx_clk are dead in the failed state, while X1 has 25MHz clock. executing software reset through the reg 0x00 clears the failed state. 

    we added to the MCU code that after every MCU reset we do a software reset. we've made 20,000 power-ups with this procedure and never got a failed state.

    our PHY's chematics:

    the data and control lines are connected directly to the STM32F107 relevant pins.

    Thanks,

    Dor.

  • 0 in reply to Dor Oliel
    TI__Mastermind 25955 points

    Hi Dor,

    We suspect is something to do witch the Microcontroller is changing the strap setting and causing a wrong strap during latch up. I would like ask some more question to double check further:

    • What MAC interface are you using?
    • Are you able to read the 25MHz clock speed from CLK_OUT pin?
    • Does your PHY freeze at the moment when it power up? or does it freeze after certain amount of time?
    • From the schematics you send to me, we saw a 4.99k ohms after the LED's which is different from datasheet recommendation. Is there any reason for that? If not, please do follow figure 6-1 in the datasheet.
    • Is there any reason why you put 33ohms increase when you connected to AVDD33? if not please do remove the that resistor and follow the figure shown below the the power setup.
    • Reference clock 25-MHz oscillator and should be in 1.8V VDDIO domain. If VDDIO is 2.5V or 3.3V, then capacitor divider needs to be used. Capacitor Recommendation: For 3.3V, CD1=CD2=27pF. For 2.5V, CD1=27pF and CD2=16pF.
    • Reset pin is active LOW, please do double check on your reset bottom design

    --

    Regards,

    Hillman Lin