DP83869HM: Setting up Digital Loopback & Confirming Results

Part Number: DP83869HM

Hi all, 

We are attempting to verify a hardware design via loopback testing. Specifically we are attempting to setup a near-end digital loopback based on information from the data sheet / forum posts.

Our System:

  • Using DP83869HM transceiver 
  • SGMII to Copper mode
  • MAC instantiated in Intel FPGA
  • MAC to PHY connection is SGMII
  • Running at 1gig speeds

Steps taken to setup digital loopback:

  • Write 0x8000 to reg 0x001F <- Performs software restart (resets PHY reg values to default)
  • Write 0x0140 to reg 0x0000 <- Sets 1000Base-T, disabled Auto-Negotiation
  • Write 0x5028 to reg 0x0010 <- Turn off auto MDI-X, put in manual mode selecting MDI-X
  • Write 0xF004 to reg 0x0016 <- Enable digital loopback, put PRBS in continuous mode
  • Write 0x4000 to reg 0x001F <- Perform software reset (preserves PHY registers values)

NOTE: We have developed some custom code to setup our PHY as per TI and Intel data sheets. This custom code executes before the above block. We have tested both with and without this custom code.

Steps taken to verify loopback is working / non-working:

  • Examine reg 0x001 (BMSR), looking for LINK_STS1 to be 1 (link up)
  • Examine reg 0x0039 (PRBS_TX_CHK_CTRL), looking for any number of error bytes
  • Examine reg 0x003A (PRBS_TX_CHK_BYTE_CNT), looking for any number of error bytes

In all cases, the link status (LINK_STS1) is down

In all cases, PRBS_TX_CHK_CTRL and PRBS_TX_CHK_BYTE_CNT registers were 0

So my questions at this point are:

  1. Are the steps listed above for setting digital loopback correct? Is there something we're missing?
  2. Are there other ways to verify if digital loopback is working?

Below is a register dump from a run in which we attempted to setup digital loopback. Note that the BMSR below indicates that the PHY link is not up, and both PRBS registers indicate 0 (error or correct) bytes received.

phy_reg_values  {...}  
    BMCR    4416    
    BMSR    31049  
    PHYIDR1 8192    
    PHYIDR2 41201  
    ANAR    481
    ALNPAR  49633  
    ANER    111
    ANNPTR  8193    
    ANLNPTR 18432  
    GEN_CFG1    768
    GEN_STATUS1 19456  
    REGCR   0  
    ADDAR   0  
    ONEKSCR 61440  
    PHY_CONTROL 20488  
    PHY_STATUS  4098    
    INTERRUPT_MASK  0  
    INTERRUPT_STATUS    40130  
    GEN_CFG2    10695  
    RX_ERR_CNT  0  
    BIST_CONTROL    4  
    GEN_STATUS2 64  
    LEDS_CFG1   24912  
    LEDS_CFG2   17476  
    LEDS_CFG3   2  
    GEN_CFG4    18  
    GEN_CTRL    0  
    ANALOG_TEST_CTRL    0  
    GEN_CFG_ENH_AMIX    0  
    GEN_CFG_FLD 0  
    GEN_CFG_FLD_THR 0  
    GEN_CFG3    0  
    RGMII_CTRL  80  
    RGMII_CTRL2 0  
    SGMII_AUTO_NEG_STATUS   3  
    PRBS_TX_CHK_CTRL    0  
    PRBS_TX_CHK_BYTE_COUNT  0  
    G_100BT_REG0    1952    
    SERDES_SYNC_STS 310
    STRAP_STS   3072    
    ANA_RGMII_DLL_CTRL  119
    RXF_CFG 4096    
    RXF_STATUS  0  
    IO_MUX_CFG  3084    
    TDR_GEN_CFG1    1874    
    TDR_GEN_CFG2    51280  
    TDR_SEG_DURATION1   21286  
    TDR_SEG_DURATION2   40990  
    TDR_GEN_CFG3    59766  
    TDR_GEN_CFG4    6607    
    TDR_PEAKS_LOC_A_0_1 0  
    TDR_PEAKS_LOC_A_2_3 0  
    TDR_PEAKS_LOC_A_4_B_0   0  
    TDR_PEAKS_LOC_B_1_2 0  
    TDR_PEAKS_LOC_B_3_4 0  
    TDR_PEAKS_LOC_C_0_1 0  
    TDR_PEAKS_LOC_C_2_3 0  
    TDR_PEAKS_LOC_C_4_D_0   0  
    TDR_PEAKS_LOC_D_1_2 0  
    TDR_PEAKS_LOC_D_3_4 0  
    TDR_GEN_STATUS  0  
    TDR_PEAKS_SIGN_A_B  0  
    TDR_PEAKS_SIGN_C_D  0  
    OP_MODE_DECODE  70  
    GPIO_MUX_CTRL   16762  
    FX_CTRL 4416    
    FX_STS  24937  
    FX_PHYID1   8192    
    FX_PHYID2   41201  
    FX_ANADV    32  
    FX_LPABL    16385  
    FX_ANEXP    3  
    FX_LOCNP    8193    
    FX_LPNP 0  
    FX_INT_EN   511
    FX_INT_STS  17  
  • Hi Neil,

    • For the setup of digital loopback could you use the following scripts:
      • 01DF 0046 //to enable SGMII to copper
        00FE E720
        0000 0140
        0010 5008
        0016 0008
        001F 4000
    • Make sure to have an extended register when you are writing the registers:
      • write procedure for MMD "1F" registers:

        write reg<000D> = 0x001F
        write reg<000E> = <address>
        write reg<000D> = 0x401F
        write reg<000E> = <value>

        read procedure for MMD "1F" registers:

        write reg<000D> = 0x001F
        write reg<000E> = <address>
        write reg<000D> = 0x401F
        read reg<000E>

        Note : To read/write MMD "1" registers, replace 1F with 01.
        Note : Above write and read procedure is normally used for registers with address greater than 0x001F. But it can also be used for any address in general.

    --

    Regards,

    Hillman Lin

  • Hi Hillman, 

    A few follow up questions for you.

    1) I see on in section 9.3.4.1 that it states "When configuring loopback modes, the Loopback Configuration Register (LOOPCR), address 0x00FE, should be set to 0xE720". This matches with your suggestion, however this register is never described or called out in any other section of the doc. Furthermore, the thread found here (https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1038106/dp83869hm-loopback-mode) implies that in most cases this register will not need to be written.

    Could you provide some clarity on what this register does, what values it accepts and how we should interact with it?

    2) This is in regards to setting reg 0x0016 to a value of 0x0008. This is the BIST register. Writing a 0x0008 puts is in analog loopback mode. We are attempting a digital loopback as suggested to do with SGMII by the data sheet. Is there a reason we should be using analog instead?

    3) Again in regards to writing reg 0x0016 to a value of 0x0008. I was under the assumption that we needed to have the PRBS enabled in order to generate packets and have them checked by the RX checker for validity. Am I misunderstanding something here?

    4) Lastly, how do we know if the loopback mode is working? Are there particular registers or values we can look at to determine if it's working / not working?

  • Hi Hillman, 

    I wanted to provide some feedback after implementing your above suggestions.

    After running with these changes we observe that the PHY link does in fact come up (where previously it did not).However we observe that the PRBS registers never increment (both show 0 in all tests).

    Is there another register I should be looking at to see if data is being transmitting in the loopback? Is there some other method of determining the results of the PRBS Tx and Rx checker?

    Here's the register dump:

    Note the PHY BMSR register indicates that the link is up. However both PRBS registers are still 0

    phy_reg_values {...}
    BMCR 320
    BMSR 31053
    PHYIDR1 8192
    PHYIDR2 41201
    ANAR 481
    ALNPAR 0
    ANER 100
    ANNPTR 8193
    ANLNPTR 0
    GEN_CFG1 768
    GEN_STATUS1 28672
    REGCR 16415
    ADDAR 59168
    ONEKSCR 61440
    PHY_CONTROL 20488
    PHY_STATUS 44034
    INTERRUPT_MASK 0
    INTERRUPT_STATUS 1088
    GEN_CFG2 10695
    RX_ERR_CNT 0
    BIST_CONTROL 8
    GEN_STATUS2 64
    LEDS_CFG1 24912
    LEDS_CFG2 17476
    LEDS_CFG3 2
    GEN_CFG4 18
    GEN_CTRL 0
    ANALOG_TEST_CTRL 0
    GEN_CFG_ENH_AMIX 0
    GEN_CFG_FLD 0
    GEN_CFG_FLD_THR 0
    GEN_CFG3 0
    RGMII_CTRL 80
    RGMII_CTRL2 0
    SGMII_AUTO_NEG_STATUS 3
    PRBS_TX_CHK_CTRL 0
    PRBS_TX_CHK_BYTE_COUNT 0
    G_100BT_REG0 1952
    SERDES_SYNC_STS 262
    STRAP_STS 3072
    ANA_RGMII_DLL_CTRL 119
    RXF_CFG 4096
    RXF_STATUS 0
    IO_MUX_CFG 3084
    TDR_GEN_CFG1 1874
    TDR_GEN_CFG2 51280
    TDR_SEG_DURATION1 21286
    TDR_SEG_DURATION2 40990
    TDR_GEN_CFG3 59766
    TDR_GEN_CFG4 6607
    TDR_PEAKS_LOC_A_0_1 0
    TDR_PEAKS_LOC_A_2_3 0
    TDR_PEAKS_LOC_A_4_B_0 0
    TDR_PEAKS_LOC_B_1_2 0
    TDR_PEAKS_LOC_B_3_4 0
    TDR_PEAKS_LOC_C_0_1 0
    TDR_PEAKS_LOC_C_2_3 0
    TDR_PEAKS_LOC_C_4_D_0 0
    TDR_PEAKS_LOC_D_1_2 0
    TDR_PEAKS_LOC_D_3_4 0
    TDR_GEN_STATUS 0
    TDR_PEAKS_SIGN_A_B 0
    TDR_PEAKS_SIGN_C_D 0
    OP_MODE_DECODE 70
    GPIO_MUX_CTRL 16762
    FX_CTRL 4416
    FX_STS 24937
    FX_PHYID1 8192
    FX_PHYID2 41201
    FX_ANADV 32
    FX_LPABL 16385
    FX_ANEXP 3
    FX_LOCNP 8193
    FX_LPNP 0
    FX_INT_EN 511
    FX_INT_STS 17

  • Hi Neil,

    • Changing register 00FE for loopback mode are design restriction.
    • Yes, you are correct. Digital loopback should be 0004 instead of 0008. Sorry for the confusion.
    • If you are running PRBS test, Try writing value F004 instead of 0004 to enable the PRBS test.
    • After running the test, make sure the register PRBS_TX_CHK_CTRL bit 0 and 1 is 1 which enable the PRBS checker and continuous mode.

    --
    Regards,

    Hillman Lin

  • Hi Hillman, 

    So in regards to setting the PRBS_TX_CHK_CTRL register. The documentation in regards to bit 0 states "PRBS TX checker is used in external reverse loop). This seems to be not our case, is there something I'm missing here?

    Making your suggested changes we still see the exact same behavior. The PRBS_TX_CHK_BYTE_CNT register is always 0. And the PRBS_TX_CHK_ERR_CNT register is also always 0. Maybe I'm not understanding how the PRBS is designed to work. My understanding is as follows:

    • Turn on PRBS generator in BIST (0x0016)
    • Let code execute
    • PRBS generator will generate frames which are sent out and looped back
    • PRBS TX checker receives looped back frames and check for accuracy
    • PRBS TX checker updates PRBS_TX_CHK_BYTE_CNT and PRBS_TX_CHK_ERR_CNT with received frames

    Is there another step I'm missing? Is there additional setup to the PRBS generator that we need to perform?

  • Hi Hillman, 

    Some more data to add.

    When we turn on PRBS frame generation via register 0x0016, we do see some statistics in the MAC registers available to us. For example, we can see that we've received a bunch of frames with a CRC error, # error frames received and total packets among others.

    So that is to say, the PRBS seems to be generating and sending frames to the MAC. However the PRBS TX / RX checker doesn't seem to be working and giving us a sense of whether or not the data is propagating properly throughout the loopback.

  • Hi Neil,

    We will check in the lab for PRBS test and provide you a response later this week. Meanwhile, could you check is your register 0x0039 bit 0 is 1 or enable the PRBS TX checker is enable?

    --

    Regards,

    Hillman Lin

  • Hi Hillman, 

    Thanks so much for taking the time to look into this, much appreciated!

    About register 0x0039. Bit 0 and 1 of this register only get set when I explicitly set them to 1. I've run a few builds where we manually set this value and see that it persists. However there was no difference in PRBS TX / RX checker results in relation to this.

  • Hi Neil,

    Just want a clarification, are you enable PRBS through MAC or internal generator. The recommendation I made earlier are all depend on the PRBS test generate through internal data generator. Did you have two 869 link up together and one board enable the reverse loopback and the other board enable the PRBS test through data generators and checker? 

    --

    Thank you,

    Hillman Lin

  • Hi Hillman, 

    We are attempting to setup a near-end, digital loopback using the PRBS.

    When you say 'enable PRBS through MAC or internal generator'. As far as I understand, the only way to enable the PRBS is via the PHY registers. So that is to say, we are enabling loopback, and enabling the PRBS via the PHY registers listed in the TI datasheet.

    Our setup is only one board. We don't connect to anything external. We would like this board to run a near-end digital loopback (so no talking to the outside world) and have the data generated by the PRBS looped back to the MAC and checked for validity by the built in PRBS checker.

  • Hi Neil,

    Thanks for clearing up the confusion. If you enable the PRBS test with internal generator, the PRBS check the signal that loop into the MAC side. Here is the diagram for further explanation: 

    --

    Regards,

    Hillman Lin

  • Hi Hillman, 

    Thanks for the diagram, this is very helpful!

    With the understanding of the diagram, we are attempting to perform a near-end digital loopback which would test the digital and PCS portions of the system.

  • Hi Neil,

    Glad that diagram help. Please let me know if you have further question.

    --
    Regards,

    Hillman Lin

  • Hi Hillman, 

    My original question still stands. With all of the information you've provided / exists in documents we are so far unable to setup loopback and see the PRBS registers increment for good and bad received packets.

    To help my understanding. Even if the physical lines are not setup correctly, if the PRBS and loopback is working correctly we would see the error counter in PRBS_TX_CHK_ERR_CNT increase. Is that correct?

    Either way we are still unable to setup the loopback properly so any additional info / steps you could provide would be greatly appreciated.

  • Hi Neil,

    Could you provide the script you wrote to enable the PRBS test and the digital loopback. I want to double check did you miss some specific steps. Meanwhile, I will also test the 869 PHY this week.

    --

    Regards,

    Hillman Lin

  • Hi Hillman,

    Here is the current set of steps we are taking to set up digital loopback and PRBS frame generation / checking

    1. Write 0xE720 to reg 0x00FE <- as called out in doc. Unsure exactly what this one does
    2. Write 0x0140 to reg 0x0000 <- GigE speed, Disable Auto-Negotiation
    3. Write 0x5028 to reg 0x0010 <- Set Manual MDI-X
    4. Write 0xF004 to reg 0x0016 <- Enable digital loopback, turn on continuous PRBS mode
    5. Write 0x4000 to reg 0x001F <- Software reset (preserving register values)
    6. Write 0x0003 to reg 0x0039 <- Continuous PRBS checker mode, Enable PRBS TX checker
  • Hi Neil,

    I will try it out in the lab and provide you a response later this week.

    --

    Regards,

    Hillman Lin

  • Hi Neil,

    We are still trying to figure out the issue you are facing for PRBS test with in the team. We might need to provide you the solution later next week. Meanwhile, Could you let me know why you need to run the PRBS test? 

    --

    Sincerely,

    Hillman Lin

  • Hi Hillman, 

    Thanks for the update!

    So we are looking to run the PRBS test so we can verify a board design we have with respect to ENET / PHY. Specifically we are looking to verify that the data lines are correct / incorrect.

    Cheers,

    Neil Ruggiero

  • Hi Neil,

    If you are verify a board design within the board. Is it possible for you to send and received packets from MAC side and enable the digital loopback on PHY? 

    --

    Regards,

    Hillman Lin

  • Hi Hillman, 

    We have some ideas for generating packets from the MAC side, but would like to be able to do so with the PRBS also.

    Cheers,

    Neil Ruggiero

  • Hi Neil,

    Is your MAC able to read the PRBS stream as well? I check with the lab last week and we were able to read the PRBS stream when we generate the PRBS stream using the internal  generator in 869PHY. Does that help with your application? 

    --

    Regards,

    Hillman Lin

  • Hi Hillman, 

    That's a great question! I will look into things on the MAC side and see if we can read the data generated by the PRBS.

    However I'm still unclear why the PRBS TX Checker bits (one for good packets, one for bad packets) are always 0. If the PRBS was working properly, wouldn't I see these registers incremented?

  • Hi Neil,

    I will discuss this issue with the design team. It might task sometime on it. I will get back to you as soon as possible.

    --

    Sincerely,

    Hillman Lin

  • Hi Hillman, 

    Just stopping by to see if there are any updates on this topic.

    Cheers,

    Neil Ruggiero

  • Hi Neil ,

    Hillman is OoO for a couple of days, and will get back to you with a response around the middle of next week.

    Sincerely,

    Gerome

  • Hi Neil,

    We are still discussing this issue internally. Are you able to receive any PRBS stream from MAC?

    --

    Regards,

    Hillman Lin