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TCAN4550-Q1: RESET impact VCCOUT

Part Number: TCAN4550-Q1
Other Parts Discussed in Thread: TCAN4550

Dear team,

In my understanding, if the customer perform a power on reset to the device via reset pin, our device will enter standby mode. In this mode, VCCOUT can output normally. But from below picture, this power on reset will impact VCCOUT. Could you please help analyze this? My customer use this VCCOUT to power MCU, this will cause the MCU to restart periodically.

Thanks & Best Regards,

Sherry

  • Hi Sherry,

    While the device will enter Standby mode with Vccout high after a reset pulse is received, the Vccout behavior is not defined during the time when RST is held high. During this time, the digital core of the device is held in reset and therefore cannot drive outputs to enable the LDO, so it will turn off during this time. 

    In order to prevent this from interrupting the supply to the MCU, the pulse time of the RST signal can be shortened (minimum 30us) to make sure the LDO turns on again quickly. If this is not possible or sufficient, the capacitance on Vccout may be increased to slow the fall time of this supply rail during the time that reset is held high. 
    Alternatively, a software reset can be done by writing to the DEVICE_RESET bit in the mode control register (h0800) to perform the same reset of TCAN4550. Because the amount of time that the digital core is held in reset is much lower using this method (no deglitch filter needed), the Vccout supply should not have time to fall noticeably before the device returns to Standby mode. 

    Let me know if you have any more questions.

    Regards,
    Eric Schott

  • Hi Eric,

    Out RST pin connects to MCU's GPIO pin. My customer found that this fault only happens when MCU's GPIO's default signal is high level. So do we have any request or recommendation for MCU's GPIO's initialized state?

    Thanks & Best Regards,

    Sherry

  • Hi Sherry,

    Is is possible to configure the default state of the GPIO pin through software? Typically GPIO pins will power-on in a high-z state. Is this not the case for this MCU?

    Are there any external biases on this signal line? The transceiver pin has an internal pull-down which should help keep the signal low when the GPIO is high-z. 

    If the default configuration of the GPIO pin cannot be changed, it may be necessary to invert the electrical signal in order to have a low-level output by default. 

    Regards,
    Eric Schott