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Original question:

SN65LVDS047: Regarding tsk(lim)

SN65LVDS047: Regarding tsk(lim)

Daisuke Higa
Genius 4340 points
Part Number: SN65LVDS047

Hi support team.

My customer asked about the following post.

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1100053/sn65lvds047-regarding-tsk-lim

Are tpLH and tpHL specified between channels, not between devices?
If so, wouldn't it be tpLH (tpHL) | max-min | < tsk (lim)?
Your answer is tpLH (tpHL) | max-min | > tsk (lim).

If my question is off the mark, I think I don't understand tsk (lim) correctly.
Is there any material that can be understood in the figure about tsk (lim)?
Also, is there any material that can understand the difference from tsk (pp) in the same way?

Best Regards,

Higa

  • 0
    TI__Guru 64326 points

    Hi Higa-san,

    tpLH and tpHL is specified for a individual lane on a single part. tsk (lim) specs the prop delay between two channel of two individual parts (Channel 0 - Channel 1 prop delay of Part A vs Channel 0 - Channel 1 prop delay of Part b). tsk(lim) takes into account process variation of prop delay between of two lanes on two different parts. 

    tsk (pp) is similar, it specs the prop delay between one channel of two individual parts (Channel 0  prop delay of Part A vs Channel 0  prop delay of Part b). This also takes into account any process variation between parts. 

  • 0 in reply to Malik Barton57
    Genius 4340 points

    Hi Barton-san

    Thank you for answering.

    I'm sorry my late response.

    I received an additional question from my customer.

    Regarding the tsk (lim) specification (maximum 1.2ns) in datasheet, the worst value is logically |tplh-tphl|=2.8ns-1.4ns=1.4ns, but it is managed to 1.2ns by test. Is our understanding correct?

    We don't understand why tsk (lim) is defined as | MIN-MAX | but the maximum is not 1.4ns.

    Best Regards,

    Higa

  • +1 in reply to Daisuke Higa
    TI__Guru 64326 points

    Hi Higa-san,

    Correct the spec was determined by test and turned out to be between than expectation of 1.4ns.