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Original question:

DS90UB960-Q1: How to use DS90UB960-Q1 EVM board to test the margin?

DS90UB960-Q1: Margin Test

guihui yang
Prodigy 100 points
Part Number: DS90UB960-Q1

We have the boar B1 and B2. B1 has TI953 and B2 has TI960.

We use the DS90UB960-Q1 EVM board to test the Margin. Here is a comparative experiment.

1.Wnen connect B1 and EVM board, the Margin test is ok.

2.When  connect B1 and B2, the Margin test is failed.

What can we get from the above test? 

According to my understanding, the purpose of margin test is to verify the stability of the physical link between ti953 and ti960. If the margin test fails, it indicates that the connection between ti953 and ti960 is unstable, which will lead to a series of problems such as lock loss, data transmission error and so on.

I wonder if there is any problem with my understanding? Please check it.

  • 0
    TI__Guru** 103215 points

    Hello Guihui,

    Do B1 and B2 board 960 devices have different I2C addresses? Why are you connecting a second 960 device to the I2C bus of the EVM? I'm trying to understand the setup

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Prodigy 100 points

    Hi Casey

    We did the margin test with the help of the EVM. We have disconnected 960 which on the EVM by pulling the PDB pin down.

  • 0 in reply to guihui yang
    TI__Guru** 103215 points

    Hello Guihui,

    It looks like based on the MAP result, the B2 board has significantly lower margin than the 960 EVM. I suspect based on the fact that the MAP is closed horizontally, that the issue is related to return loss being insufficient in the high speed layout path. As you say, this will lead to worse performance of the high speed link, parity errors, or possibly loss of LOCK during operation. If you want to share your high speed layout design we can review and provide suggestions on how to improve. 

    Best Regards,

    Casey