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DS125DF1610: the link status of Panel 10 GBIT/s optical module is not stable. the retimer is Ds125df1610.

yunpu tian
Prodigy 20 points
Part Number: DS125DF1610
Other Parts Discussed in Thread: DS125MB203

Hi TI，

   The hardware channels are as follows: mainboard switch 《-》backplane 《-》 Ds125df1610《-》ds125mb203 《-》Panel 10 GBIT/s optical module.It can be configured through i2C channels DS125DF1610 and DS125MB203.

  The problem is:  the panel optical port is  link (self-loop and docking other devices) ,but when connecting  tol the spirent N11u FX2 2-port 40/10GBE qsfp+, linking is down. sometimes, linking is gonna be ok after sereval minutes slowly. so, could you help me confirm the registers configure of the  Ds125df1610?  I pick up    port30  from   all ports to connect to spirent N11u. the port30 matchs the channel 2 and 10 of Ds125df1610. 

share regisers :root@ebang:/tmp/app$i2cdump -f -y 19 27
       0   1   2   3  4    5   6  7   8    9   a   b   c   d  e   f  0123456789abcdef
00: 00 71 00 00 01 08 00 05 00 00 01 50 00 0d 01 ff .q..??.?..?P.??.
10: FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0:  00 00 00 00 00 00 00 00 00 00 00 00 00 04 03 00 .............??.
root@ebang:/tmp/app$

channel 2:root@ebang:/tmp/app$i2cdump -f -y 19 27
       0   1   2   3   4   5  6   7   8   9   a    b  c   d   e   f   0123456789abcdef
00: 00 80 dc 00 01 01 01 01 60 00 50 6f 08 b4 93 69 .??.????`.Po???i
10: 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e9 55 : ??.?z6@ ???.?U
20: 00 00 00 40 00 02 08 10 16 00 30 0f f2 04 00 b6 ...@.????.0???.?
30: 00 20 11 88 bf 1f 30 03 00 00 00 33 8e 35 43 c7 . ????0?...3?5C?
40: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90 .???@?????0AP?`?
50: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5 ???FR???W]iu????
60: 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 00 ....... .?"@....
70: 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a ? ...."?0?...H?:
80: 17 e4 00 00 00 00 00 00 00 00 00 00 00 02 1c 10 ??...........???
90: 00 00 00 00 00 00 04 00 0c 3f 3f 00 d5 99 96 a5 ......?.???.????
a0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90 .???@?????0AP?`?
b0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5 ???FR???W]iu????
c0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90 .???@?????0AP?`?
d0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5 ???FR???W]iu????
e0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90 .???@?????0AP?`?
 f0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 04 00 03 01 ???FR???W]iu?.??

channel 10: root@ebang:/tmp/app$i2cdump -f -y 19 27
      0   1   2   3   4   5   6   7   8   9   a   b   c   d  e   f      0123456789abcdef
00: 00 80 dc 00 01 01 01 01 60 00 50 6f 08 b4 93 69 .??.????`.Po???i
10: 3a 20 e0 90 00 12 7a 36 40 20 a0 03 90 00 e9 55 : ??.?z6@ ???.?U
20: 00 00 00 40 00 00 00 2b 78 40 30 0f f2 07 00 b6 ...@...+x@0???.?
30: 00 20 11 88 bf 1f 30 15 00 00 00 33 8e 2e 00 20 . ????0?...3?..
40: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90 .???@?????0AP?`?
50: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5 ???FR???W]iu????
60: 00 00 00 00 00 00 00 20 00 0a 22 40 00 00 00 00 ....... .?"@....
70: 03 20 00 00 00 00 22 1a 30 10 00 00 00 48 13 3a ? ...."?0?...H?:
80: 00 e4 00 00 00 00 00 00 00 00 30 00 00 02 1c 8c .?........0..???
90: 00 00 00 00 00 00 04 00 0c 3f 3f 00 d5 99 96 a5 ......?.???.????
a0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90 .???@?????0AP?`?
b0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5 ???FR???W]iu????
c0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90 .???@?????0AP?`?
d0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5 ???FR???W]iu????
e0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90 .???@?????0AP?`?
f0:  88 82 a0 46 52 8c b0 c8 57 5d 69 75 00 04 03 01 ???FR???W]iu.???
root@ebang:/tmp/app$

and   the attenuation that your PCB   is as follows:

hostboard to backplane : -7.54723 db

backplane :-2.99692db

backplane to retimer :-3.53349db

retimer to sfp:-3.33074db

  • 0
    TI__Mastermind 19235 points

    Hi,

    Based on the register logs you shared retimer channel 2 somehow shows poor eye opening values. Perhaps this explain the link issues you are observing. I would recommend to implement retimer adapt mode 2 (i.e. DFE enabled in addition to CTLE) to improve eye margin. See below:

    Table. Adapt mode 2, enable the DFE

     

    STEP

     

    SHARED/CHANNEL REGISTER SET

     

    OPERATION

    REGISTER ADDRESS [HEX]

    REGISTER VALUE [HEX]

    WRITE MASK [HEX]

     

    COMMENT

    1

    Channel

    Write

    31

    40

    60

    Adapt Mode = 2

    2

    Channel

    Write

    1E

    00

    08

    Enable DFE (DFE_PD=0)

    Note: A CDR reset and release operation is recommended when changing the retimer EQ settings

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    first,I appreciate for your timely reply,and you answers work nicely to my questions,it's sovled almostely. All port linkings are ok. but I also have some questions that needs your explanation.

    (1) there is two channels for each port, one to backplane and another to optical module. you know, from my real experiments data, the registers'values in the two channels of each port  should not be the same,such as follows:

    so I have a problem that how to use a simple method to  initiate all channels's regisers  for a slot board。if all channel's register's value are same , you know, i can do a batch ops through register 0xff,0xfc,0xfd. but now for the two channels of each port,the register's value are not  same. how do i do that?

    (2) there is a strange thing for 0x15 register. for example: there are FCS in the port 29 's receiving direction,then I change 0x15 from value 0x10 to value 0x13 in the port30's sending direction,you know,port 30 is connecting with port 29. FCS in the port 29 's receiving direction are disappeared. then I change 0x15 from value 0x13 to value 0x10 in the port30's sending direction,FCS in the port 29 's receiving direction are also disappeared. why?

    ops are as follows"

    register 0x15 is 0x10 （FCS）->set  0x15 to 0x13-》set 0xa to 0x5c-》set 0xa to 0x50 （no FCS）-》set  0x15 to 0x10-》set 0xa to 0x5c-》set 0xa to 0x50（no FCS）

    （3）there is always one or two ports that having several FCS in the continuous tesing for one day . do you have some suggestion for the phenomenon? port 29's register's value list is as follows:

    3,29,19,0x27,0,1,0x31,0x40;
    3,29,19,0x27,0,1,0x1e,0xe1;
    3,29,19,0x27,0,1,0xa,0x5c;
    3,29,19,0x27,0,1,0xa,0x50;
    3,29,19,0x27,0,1,0xa,0x5c;
    3,29,19,0x27,0,1,0x2f,0xb6;
    3,29,19,0x27,0,1,0x15,0x10;
    3,29,19,0x27,0,1,0x2d,0x88;
    3,29,19,0x27,0,1,0x3d,0x35;
    3,29,19,0x27,0,1,0x12,0x76;
    3,29,19,0x27,0,1,0x3e,0x43;
    3,29,19,0x27,0,1,0x3f,0xc7;
    3,29,19,0x27,0,1,0xa,0x50;
    3,29,19,0x27,0,9,0x31,0x40;
    3,29,19,0x27,0,9,0x1e,0xe1;
    3,29,19,0x27,0,9,0xa,0x5c;
    3,29,19,0x27,0,9,0xa,0x50;
    3,29,19,0x27,0,9,0xa,0x5c;
    3,29,19,0x27,0,9,0x12,0xe0;
    3,29,19,0x27,0,9,0x15,0x12;
    3,29,19,0x27,0,9,0x2d,0x07;
    3,29,19,0x27,0,9,0x2f,0xb6;
    3,29,19,0x27,0,9,0x3d,0x2e;
    3,29,19,0x27,0,9,0x3e,0x00;
    3,29,19,0x27,0,9,0x3f,0x20;
    3,29,19,0x27,0,9,0xa,0x50;
    3,29,19,0x27,0,9,0x15,0x13;
    3,29,19,0x27,0,9,0xa,0x5c;
    3,29,19,0x27,0,9,0xa,0x50;

  • 0 in reply to yunpu tian
    Prodigy 20 points

    you know, the  priority of FCS in the continuous testing  is high. so you could deal with the question of the number (3) firstly .thank you!

  • 0 in reply to yunpu tian
    TI__Mastermind 19235 points
    1. All retimer channels should default to the same register settings. Are you configuring channels differently? The user has the option to use the same register settings across retimer channels. Also, the user may enable broadcast write option to implement the same write to all retimer channels. see below
    2. Below for ease of reference is the channel register 0x15 description. Bits 1:0 affect the retimer tx output amplitude. This degeneration parameter effective adds attenuation thus reducing the output amplitude. Most likely you are not using optimal settings for the retimer Tx output amplitude and/or tx FIR taps and that's why BER is changing. Please refer to DS125DF1610 datasheet Section for details on how to configure the output amplitude. In addition, refer to the datasheet register table and look at channel registers 0x3D, 0x3E and 0x3F
    3. It's difficult for me to debug without seeing values for retimer status registers.
      • Please provide read values for the following channel registers for the case where FCS errors are being observed: 0x02, 0x27, 0x28, 0x71, 0x72, 0x73, 0x74, 0x75, 0x78, and 0x8F 

    Thanks,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Prodigy 20 points

    first ,thank you for your timely replay.

    1. I can confirmly tell you that I have configured channels differently. you know,if I would have configured channels the same values, There're many problems coming,such as linking down,fcs 。。。。

    two channel for port 14 () is channel 0 and channel  8:

    channel 0:

    channel 8:

    from the above photos,you know, two channels for one port are configured different register values.

    and you talked about the channel registers 0x3D, 0x3E and 0x3F ,0x15 last time,  but what values do I should configure for these registers?

    and about the fcs problem in 10G mode,I found a method to resovle it. the cause of fcs is channing the port mode for sgmii to xfi after retimer configure finished,at this situation,It's easy for retimer to lock unstablly. so I think: first configure port mode,second configure retimer regisgers. the configure sequence is very important. so If port mode changed, need to configure retimer regisgers again.

    2. Now there is a new problem that when one port configuring a xfi mode,the link is up;but when configuring a sgmii mode ,the link is down, why? In my opinion, for one port ,whatever configuring xfi mode and sgmii mode,  the registers values of the two retimer's channels are same,not change, so the link status should be same. I remember when I debug this retimer chip on the fird day,I found 1G link is ok so easily,but now I focus on 10G linking problem for a long time, I ignored the 1G link. I confused with 10G link and 1G problems. is there a relationship between 10G link and 1G ?

    for port 14 , its 10G link is ok,but 1G link is down. the the registers values of the two retimer's channels of the port 14 are displayed in the above two photos.

    thank you, look forward to you timely relpy!

  • 0 in reply to yunpu tian
    Prodigy 20 points

    the latest discovery is that channel register 0x1e 's bit[3] DEF_PD is the key bit. when set register 0x1e to value 0xe9, 1G mode link is up;and when set register 0x1e to value 0xe1, 10G mode link is up. why???

  • 0 in reply to yunpu tian
    TI__Mastermind 19235 points
    1. Related to: "and you talked about the channel registers 0x3D, 0x3E and 0x3F ,0x15 last time,  but what values do I should configure for these registers?"
      • These registers configure the retimer Tx output amplitude and de-emphasis levels. The optimal levels depend on your system channel and requirements
    2. Now there is a new problem that when one port configuring a xfi mode,the link is up;but when configuring a sgmii mode ,the link is down, why? In my opinion, for one port ,whatever configuring xfi mode and sgmii mode,  the registers values of the two retimer's channels are same, not change, so the link status should be same. I remember when I debug this retimer chip on the fird day,I found 1G link is ok so easily,but now I focus on 10G linking problem for a long time, I ignored the 1G link. I confused with 10G link and 1G problems. is there a relationship between 10G link and 1G ?
      • The CDR standard rate setting for 1G and 10G Ethernet is the same and as follows
        • channel register 0x2F[7:4]=0xB
      • If the retimer is locked to 10GE data and input data is subsequently switched to 1GE data you may need to perform a retimer CDR reset and release operation to restart the CDR locking and EQ adaption at the new rate

    Thanks,

    Rodrigo Natal

  • 0 in reply to yunpu tian
    TI__Mastermind 19235 points

    It seems unusual that simply powering down the DFE would be the difference between locking to 1G vs 10G data. Do please try implementing retimer CDR reset and release operation when changing from 1G to 10G Ethernet rates or vice versa and see whether you no longer run into problem.

    Thanks,

    Rodrigo Natal