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DS100DF410: DS100DF410 schematic review

Part Number: DS100DF410

Hi Team,

 Would you help review customer schematics with two DS100DF410SQ in SMBus master mode? thanks a lot. 

Thanks & Regards

Eddie

  • Hi Eddie,

    Please note that this is a public forum.  It might be advisable to move this to an internal forum.

    Regarding the schematic review, please find my notes below:

    • VDD decoupling caps (Good)
    • HS I/O: Please ensure that there on AC coupling caps in the signal chain on both the RX and TX pins of the DS100DF410
    • REFCLK (Good)
    • It appears that the two devices share the same READ_EN net.  This should not be the case in SMBUS master/controller mode.  Please see section  7.4.1 and Figure 5 in the datasheet.
    • SDA/SCL (Good)
    • EEPROM Address (Good)
    • SMBus Address (Good)
    • LPF_REF/LPF_CP (Good)

    Thanks,

    Drew

  • Hi Eddie,

    Please note that this is a public forum.  It might be advisable to move this to an internal forum.

    Regarding the schematic review, please find my notes below:

    • VDD decoupling caps (Good)
    • HS I/O: Please ensure that there on AC coupling caps in the signal chain on both the RX and TX pins of the DS100DF410
    • REFCLK (Good)
    • It appears that the two devices share the same READ_EN net.  This should not be the case in SMBUS master/controller mode.  Please see section  7.4.1 and Figure 5 in the datasheet.
    • SDA/SCL (Good)
    • EEPROM Address (Good)
    • SMBus Address (Good)
    • LPF_REF/LPF_CP (Good)

    Thanks,

    Drew

  • Hi Drew,

    Thanks for suggestion. 

    Best Regards

    Eddie