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DP83826I: Power up sequence

franziskus
Expert 8559 points
Part Number: DP83826I


Team,

my customer has a question about the sequence of the AVDD3V3 and VDDIO voltages. They are powering the device up in the following sequence and wanted to undertstand if this is ok:

  1. VDDIO starts with 1.8V.
  2. A few milliseconds after that, AVDD3V3 starts with 2.5V
  3. Some hundret milliseconds later, AVDD3V3 is going to 3.3V

During this time, the PHY is held in reset by a GPIO with pull-down. They are planning to release the reset after all voltages are initialized correctly.

Best regards

  • +1
    TI__Expert 3727 points

    Hi Franziskus,

    All timing and start-up requirement are listed in the datasheet.

    Please make sure the customer has all criteria met to insure correct operation. 

    Best,

    Alon 

  • 0 in reply to Alon Kopelman
    TI__Expert 8559 points

    Hi Alon,

    thanks for your answer! I guess the main point in my question is the following:

    • Since their AVDD3V3 is first ramping to 2.5V and later to 3.3V, I guess that the overall time to 3.3V should not exceed 200msec, correct?
      • Is the intermediate step to 2.5V an issue?
    • Does the power up timing apply if the device is kept in reset the entire time and is only released when all voltages are stable?

    Best regards

  • +1 in reply to franziskus
    TI__Expert 3727 points

    Hi Franziskus,

    Yes, shouldn't be a problem as long as you don't exceed 200ms. 

    What do you mean 

    franziskus said:
    Does the power up timing apply if the device is kept in reset the entire time and is only released when all voltages are stable?

    How are you in reset if the device isn't powered up? do you mean you have reset signal on the entire start up time? I am not sure what are the implications of doing that but I don't see why that should be an issue.

    Best,

    Alon 

  • 0 in reply to Alon Kopelman
    TI__Expert 8559 points

    Hi Alon,

    thanks! Correct, they keep the RST_N pin LOW the entire start-up and only release it after AVDD3V3 is at 3.3V.

    Does the 200msec requirement apply in this case as well?

    Best regards

  • +1 in reply to franziskus
    TI__Expert 3727 points

    Hi Franziskus,

    I don't believe it should cause any issues, however, given that it is not directly addressed in datasheet, i cannot guarantee it, I will ask the team later and will update if I have a more concrete answer.

    By default I wouldn't recommend doing this, however, if customer tests it and it works then I don't see a reason it should cause further issues given you release the reset during the right timing. 

    Best,

    Alon

  • 0 in reply to Alon Kopelman
    TI__Expert 8559 points

    Thank you Alon!

  • 0 in reply to franziskus
    TI__Expert 8559 points

    Alon,

    I do have a follow-up question:

    Unfortunately, my customer cannot raise the AVDD3V3 until about 500-700ms after turning on VDDIO from 2.5V to 3.3V. This is clearly above the maximum of 200ms, but I still wonder what problems to expect if they exceed this limit each time they turn on the system. They may be able to correct the initialization later in case of a faulty initialization.

    Best regards

  • +1 in reply to franziskus
    TI__Expert 3727 points

    Hi Franziskus,

    If you do not meet the timing requirements outlined by the datasheet, you risk getting the PHY's state machine being stuck at an unknown state. 

    There would not necessarily be a way to fix it without turning PHY off and reinitializing with correct procedure. 

    Best,

    Alon

  • 0 in reply to Alon Kopelman
    TI__Expert 8559 points

    Hi Alon,

    ok, understood!

    New idea: When the are using the internal LDO to supply VDDIO, do you see any issue with their AVDD3V3 first going to 2.5V and then going to 3.3V after 500-700msec?

    Best regards

  • +1 in reply to franziskus
    TI__Expert 3727 points

    Hi Franziskus,

    Every datasheet requirement must be met in order to insure correct operation of the PHY, if the datasheet does not specifically address this, then we can only comment on what happens after you try it, because we have not tested these conditions in house, we have no way to predict how the PHY will react.

    In theory, if the datasheet doesn't say you can't do this, and you are meeting all power-ramp requirements, then in theory I cant think of a reason it shouldn't work. 

    Best,

    Alon