AM62x: What can be the immediate layer on top of MAILBOX ?

Hello AJITHKUMAR, 

Please provide more information.  What TI device is this in reference to?  Please provide as much information as possible about the design.

Thank you.

~Leonard  

Hi Leonard ,

The soc in discussion is the AM62X family .

Can you provide some more detail/context for your question please? It's not very clear what specifically you are asking.

Regards, Andreas

Let me put it this way ,In TI technical reference documents I have noticed that the IPC communication involves use of MAILBOX( to trigger interrupts )and a Vring to access the shared memory to read and write data that needs to be transferred between cores .

Do we use the same API's to trigger the interrupts and transfer data via shared memory or different API calls ?

Does mailbox as its own API to trigger interrupts or will it use IPC_Notify API's ?

If MAILBOX is used as physical layer to trigger interrupts what will be the immediate media or data layer on top of it ?Is it SW specific ?

Hello,

What inter-processor communication (IPC) does TI currently support on AM62x?
TI currently supports RPMsg on AM62x for sending messages between the Linux A53 cores and the M4F core, assuming that the M4F core is being used as a general purpose processor. Note that if M4F is being used for safety, then it is isolated from the rest of the processor and is NOT able to use RPMsg to communicate with the A53. There are other ways to implement IPC, and you can develop other IPC methods on your own if you want. This is just the version of IPC that TI has tested and supports.

Let's make sure you are finding the appropriate documentation.

Linux Academy for AM62x: "Evaluating Linux" sections "Booting remote cores" and "Tour of TI Linux > IPC" coming soon: https://dev.ti.com/tirex/explore/node?a=7qm9DIS__8.1.0.0%20v1&node=AO2IbV53aUarnRvmyK9fxQ__XaWts8R__LATEST 

Linux SDK side documentation: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/08_03_00_19/exports/docs/linux/Foundational_Components_IPC62x.html

MCU+ SDK side documentation: https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/08_03_00_07/exports/docs/api_guide_am62x/IPC_GUIDE.html, https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/08_03_00_07/exports/docs/api_guide_am62x/DRIVERS_IPC_RPMESSAGE_PAGE.html, https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/08_03_00_07/exports/docs/api_guide_am62x/EXAMPLES_DRIVERS_IPC_RPMESSAGE_LINUX_ECHO.html

Let's talk about IPC Implementation Details

IPC_RPMsg on the M4F side is used to send messages to and from the Linux RPMsg driver. There is a lower-level M4F driver called IPC_Notify that is specifically sending the mailbox messages that are used for RPMsg communication. However, from the Linux side the low-level mailbox drivers have not been exposed up to userspace. That means TI does not currently support the M4F using IPC_Notify to send only a mailbox message to Linux. (On processors with multiple MCU+ cores, like AM64x, MCU+ cores can use IPC_Notify to send mailbox messages to other MCU+ cores).

If you were looking to use shared memory to pass information between cores, we do not yet have a TI example for this. However, the example would look like this:
* define a shared memory region in the Linux devicetree
* if userspace needs access to this shared memory region, either need elevated permissions (e.g., using /dev/mem to directly access the memory, easiest to start development), or expose the memory to userspace (e.g., with a small UIO or character driver)
* IPC_RPMsg is used for signaling between cores (e.g., for one core to notify the other that the data in the shared memory region is ready)

Regards,

Nick