• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 33 subscribers
  • Views 300 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB947-Q1: DS90UB947-Q1 + DS90UB948-Q1 series x8 pcs chain

Sergej Dziuba
Prodigy 50 points
Part Number: DS90UB947-Q1

Dear Representative,

We are working on project which may consist of chain from x8 series links. Each link is TX+RX. where: TX is DS90UB947-Q and RX is DS90UB948-Q, here I attached simple diagram for understanding:

Can you please advice, will this configuration work:

1. from I2C bus point of view?

2. from I2S bus point of view?

Because in datasheet noted, what the maximum possible configuration is(see image below):

Thank you!

Looking forward your answer!

Sergej.

  • 0
    TI__Mastermind 18046 points

    Hi Sergej, 

    From the I2C and I2S point of view there should not be a problem. However, there is a bigger issue with the system. We do not recommend implementing this configuration due to low frequency jitter accumulation across the OLDI links. As with each series link, the jitter accumulates and does not meet the total jitter and skew input specs for the 947 which is really hard to control in mass production. 

    Best,

    Shu

  • 0 in reply to Shu Huang
    Prodigy 50 points

    Shu, thank you for the fast reply!

    1. If we add FPGA between RX and TX in each link - can it help us to solve jitter problem?(see configuration image below). Because in such way in each link we have new source of LVDS data.

    Another buses like I2C/I2S will be connected as in previous configuration directly from RX to TX.

    Thank you!

    Looking forward your answer!

    Sergej.

  • 0 in reply to Sergej Dziuba
    TI__Mastermind 18046 points

    Hi Sergej, 

    This can work as long as the FPGA is providing a clean clock and data output to the 947 and meeting the input jitter specs in between each link. 

    Best,

    Shu

  • 0 in reply to Shu Huang
    Prodigy 50 points

    Thank you, Shu!

    I have additional question: in such series configuration with FPGA between RX and TX, as I showed above in last question, we use RX and TX in "repeat mode", and connect I2C and I2S directly from RX to TX without FPGA, but video data by LVDS will go through FPGA. Can such connection insert some shift between voice and video? Thank you!

  • 0 in reply to Sergej Dziuba
    TI__Mastermind 18046 points

    Hi Sergej, 

    This is a possibility as adding the FPGA introduces some latency for the video. 

    Best,

    Shu