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DP83867IR: 100 Mbps Synchronous Clocks

Ryan Gill
Prodigy 20 points
Part Number: DP83867IR

Hello,

I am using the DP83867 Ethernet PHY chip in MII mode at 100 Mbps speed. I have a board with 3 of these PHY's on it all being driven by the same 25 MHz crystal oscillator. When I probe their TX_CLK outputs they are all at the correct 25 MHz, but they are out of phase with each other. I want the TX_CLK on all of the PHYs to match each other and match the crystal oscillator. I want them to be in phase with the oscillator. Is this possible with this chip in 100 Mbps MII mode? If so, how does the chip need to be configured to accomplish this (hardware or register wise)? I also have this chip on other boards that connect to this board through ethernet cables. I want the PHY's on the other boards to pull the RX_CLK off of the receive packets and then set their TX_CLK to that of the RX_CLK. That way everything is synchronized to the oscillator on the main board in a master/slave topology. Is this possible with this chip in 100 Mbps MII mode? If so, how does the chip need to be configured to accomplish this (hardware or register wise)? I see that the datasheet mentions a register for setting the chip in master/slave mode, but it only talks about this in context of 1000 Mbps, does this work with 100 Mbps as well?

Thanks,

Ryan

  • +1
    TI__Mastermind 39855 points

    Hi Ryan,

    There is a PLL that is not locked to the phase of the XI clock. This will explain why 3 different PHYs have different phase alignments even while sourcing the same clock signal.

    We do offer within 2ns phase lock on DP83826. It appears that DP83867 is overkill for your use case application (100mbps using MII). DP83826 would be able to meet the use case as well as offer that tighter phase lock.

    Sincerely,

    Gerome

  • +1 in reply to Gerome Cacho
    Prodigy 20 points

    Thank you Gerome!

  • 0 in reply to Gerome Cacho
    Prodigy 20 points

    Hi Gerome,

    What about the second part of my question: is it possible to lock the tx clock to the rx clock in a sort of slave mode at 100 mbps MII?

  • 0 in reply to Ryan Gill
    TI__Mastermind 39855 points

    Hi Ryan,

    Please allow me to get back to you.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    TI__Mastermind 39855 points

    Hi Ryan,

    We have never characterized this to work in this condition. As such, the responsibility would be yours to validate such a configuration.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 20 points

    Hi Gerome,

    Thank you for getting back to me. The part you suggested that I use instead: DP83826, the TX CLK will be phase locked to the reference and out of phase by 4 ns maximum. That solves half of my problem. If I have a few of these DP83826 PHYs on one board all synced to the same reference clock, then their TX clocks will all be synced within 4 ns. If I have a bunch of these DP83826 PHY's on other boards with a one to one connection, the RX clock they pull off, will it also be synced to a certain degree? Or will the RX clock be phase locked, but the starting phase may vary? I bought 2 eval boards for this chip, and I am seeing the TX clk remain 4 ns in phase across power cycles like you have said it would. However, the starting phase on the RX clock on the other board is jumping around. Its locked to tx clock on board one, but it seems like it can be an entire cycle out of phase and its not consistent across power cycles. Meaning my multiple RX clocks on multiple PHYs would not be synced.

  • +1 in reply to Ryan Gill
    TI__Mastermind 39855 points

    Hi Ryan,

    Unfortunately, this seems to be a fundamental system issue. The RX_CLK is clock divided from the MDI datastream, and thus would have no way of knowing which clock edge to start the division from, thus explaining the phase jumping on the other board.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 20 points

    Thank you Gerome!

  • 0 in reply to Gerome Cacho
    Prodigy 20 points

    Hi Gerome,

    One more question. The spec for the DP83826 says the latency from the rising edge of the reference to the rising edge of the TX CLK is max 4 ns. The latency from the rising edge of the TX CLK to the SSD symbol on MDI is 38 - 40 ns for a 100 meter cable. Does that mean for a theoretical 0 meter cable it would be 2 ns (40 - 38)? And then the latency from SSD symbol on MDI to rising edge RX CLK is 166 - 170 ns for a 100 meter cable. Does that mean for a theoretical 0 meter cable it would be 4 ns (170 - 166). So then if we were using theoretical 0 meter cables, the max delay from rising edge on the reference on one board to the rising edge of the RX CLK on the other board would be 10 ns (4 + 2 + 4)?. Therefore, is it safe to assume that in my setup of multiple PHYs on board 1 being driven by the same reference, the PHYS they are connected to on other boards (if all connections have the same cable length), their RX CLK's rising edge's should be within 10 ns of each other?

  • 0 in reply to Ryan Gill
    TI__Mastermind 27042 points

    Hi Ryan,

    Gerome is out of office this week and will get back to you by early next week.

    Thanks,

    David

  • 0 in reply to David Creger
    Prodigy 20 points

    Hi David. Ok thank you. On the topic of help with this: do you know of any consulting services that are experts in TI PHY chips?
    Thanks,

    Ryan

  • 0 in reply to Ryan Gill
    TI__Mastermind 27042 points

    Hi Ryan,

    What kind of service are you looking for?

    Thanks,

    David

  • 0 in reply to David Creger
    Prodigy 20 points

    An engineering consultant that can help us with a board/system design using these chips. Help point out common practices and common pitfalls. Etc.

  • 0 in reply to Ryan Gill
    TI__Mastermind 27042 points

    Hi Ryan,

    We use Krypton Solutions for board design. Recommend using our EVM as a a reference design, schematic is found in the user's guide.

    Thanks,

    David