This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB949-Q1: DS90UB949-Q1 EDID ?

Part Number: DS90UB949-Q1

Question 1:

1.Can the internal EDID of 949 be overwritten?

At present, we can only read this data but cannot rewrite it (the EDID is read as shown in the figure below).

If it can be rewritten, please tell us the method (whether it is necessary to set registers or what kind of hardware design is required)?

Question 1:We installed an EEPROM on DS90UB949-Q1 and wrote it into EDID.

However, after power on, the PC couldn't read the EDID through HDMI.

Could you please change the hardware or storage to solve this problem. Our hardware is as follows

  • Hi Kevin, 

    Thank you for your question, I will take a look and get back to you by the end of the week. 

    Best,

    Shu

  • Hi Kevin, 

    The internal EDID can be overwritten, please see this E2E thread for example script: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/606928/ds90ub949-q1-how-to-change-the-edid-value

    As for the external EEPROM, I am unable to see the schematic in close detail, can you attach it as a pdf? One thing I would like to check would be for the strap mode of the 949 to know that there is an external EDID. 

    Best,

    Shu

  • Question 1: we use DDC_ SAD/DDC_ I2C channel of SCL, edit EDID, but failed. Edit device address 0x50 (EDID as attachment.H). Please help confirm whether there are 949 registers to be set?
    const unsigned char ucBinToTextBuf[]={

    /*00000000H:*/0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x0F,0x23,0x46,0x01,0x00,0x00,0x00,0x00,
    /*00000010H:*/0x00,0x19,0x01,0x04,0xA5,0x1C,0x10,0x78,0xEA,0x5D,0x45,0x96,0x58,0x52,0x98,0x27,
    /*00000020H:*/0x26,0x50,0x54,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
    /*00000030H:*/0x01,0x01,0x01,0x01,0x01,0x01,0x44,0x35,0x80,0x78,0x70,0x38,0x22,0x40,0x28,0x28,
    /*00000040H:*/0x82,0x00,0x40,0x44,0x21,0x00,0x00,0x1A,0x00,0x00,0x00,0xFC,0x00,0x47,0x30,0x36,
    /*00000050H:*/0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x10,0x00,0x00,
    /*00000060H:*/0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,
    /*00000070H:*/0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC2,
    /*00000080H:*/0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /*00000090H:*/0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /*000000A0H:*/0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /*000000B0H:*/0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /*000000C0H:*/0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /*000000D0H:*/0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /*000000E0H:*/0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    /*000000F0H:*/0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
    };
    Question 2: PDF is attached
  • Hi Kevin, 

    Based on the schematic hardware strap modes, the device is configured to check for remote EDID to be loaded. 

    The 949 has several registers to be configured for remote EDID, the fields are described and listed in the datasheet. Below are the registers needed:

    0x4F BRIDGE_CTL - EDID INIT may be set to reload EID SRAM

    0x50 BRIDGE_STS - Status register, Read only

    0x51 EDID_ID - make sure the I2C address of the EDID device is written to this register

    0x52 and 0x53 are EDID_CFG registers to modify the hold times 

    Can you share what these are set to?

    Best,

    Shu

  • Shu:

    It seems that our hardware design needs to be modified. We need to set the mode to load the EDID of the local EEPROM. How can we modify our hardware?

    How to set the register of synchronization 494?

    The register information of initialization 494 is as follows:

    Register 0X4F :  value 0X00

    Register 0X50:value 0X97

    Register 0X51:value 0XA1

    Register 0X52:  value 0X1E

    Register 0X53: value 0X00

  • Hi Kevin, 

    In order to load from the internal SRAM, resistor R25 for MODE_SEL1 should be removed and adhere to the following mode strap setting. 

    How to set the register of synchronization 494?

    Can you clarify on this? I am not sure what synchronization is referring to. 

    Best,

    Shu

  • Shu:

          Q1 :How do I modify hardware to use external local EDID ?

          Q2: Please provide 949&948 initialization Settings.

          Q3: After we remove R25, the computer can recognize the EDID(external local EDID)  through HDMI, but 948 is unlock. Please help to analyze the problem

  • Hello Kevin,

      Q1 :How do I modify hardware to use external local EDID ?

    To use external local EDID, strap MODE_SEL0 = #3 and set MODE_SEL1 = #1. Yu must also populate an EEPROM device attached to the DDC pins of the 949. The EEPROM must have the desired EDID loaded into it by some other external means. 

          Q2: Please provide 949&948 initialization Settings.

    This is a very broad question. In general for basic video setup as long as you have mode strapped the device to the correct mode, and there is an EDID available to match your panel spec, then the process should be totally automatic to get display running

        Q3: After we remove R25, the computer can recognize the EDID(external local EDID)  through HDMI, but 948 is unlock. Please help to analyze the problem

    MODE_SEL0 needs to be strapped to #3 for external local EDID mode. You can use pullup of 82.5k, and pull down of 102k for the MODE_SEL0 pin to set this. Also, what is the panel spec you are trying to drive? What resolution/PCLK? It looks from the EDID like 1920x1080. Is your HDMI source recognizing a 1920x1080 sink when you strap the modes correctly and plug the HDMI in?

    Best Regards,

    Casey 

  • kevin.huang_FJXM said:

        Q3: After we remove R25, the computer can recognize the EDID(external local EDID)  through HDMI, but 948 is unlock. Please help to analyze the problem

    MODE_SEL0 needs to be strapped to #3 for external local EDID mode. You can use pullup of 82.5k, and pull down of 102k for the MODE_SEL0 pin to set this. Also, what is the panel spec you are trying to drive? What resolution/PCLK? It looks from the EDID like 1920x1080. Is your HDMI source recognizing a 1920x1080 sink when you strap the modes correctly and plug the HDMI in?

    Q4:

    MODE_SEL0 needs to be strapped to #3 :We use pull up of 82k, and pull down of 100k for the MODE_SEL0 pin to set this, and measurement voltage of VR4 is 0.983V.

    MODE_SEL1 needs to be strapped to #1 : we remove R25.

    The panel resolution is 1920 ×1080 and PCLK is 136.36 MHzthe EDID file is made by AWEDIDEditor.exe

    After setting the pin of MODE_SEL0/1 as you suggested, we find that 948 is unlock.

    When we connect PC with 494 through HDMI cable, 498 is unable to communicate through I2C. (When we remove HDMI cable, 498 is able to communicate through I2C).

    What do we need to do to solve 948 unlock & I2C communication?

  • Hi Kevin, 

    Can you share the schematic on the 948 side?

    Best,

    Shu

  • Hi Kevin, 

    Can you share the entire schematic? The above screenshot has elements cropped out. 

    Best,

    Shu

  • Shu

       Sorry, the PCB board of 948 is designed by the customer, so we can't get all the information. If you have any partly Settings that you want to confirm, we can try to get them.

  • Hi Kevin, 

    I would like to check the MODE_SEL of the 948. Is it possible for you to get the register configurations for the 948? A register dump would be helpful in trying to figure out why the link is dropping. 

    Best,

    Shu

  • Shu:

         The register configuration is as follows on the 948 side

           Register 0x49 ,value 0x60.( Only this register is configured)

         The MODE_SEL of the 948 as follows(MODE_SEL0: Vmode=0V;   MODE_SEL1: Vmode=1.245V;). These are actually measured.

  • Hi Kevin, 

    Making sure I understand the situation, when HDMI is connected, the link between the 949 and 948 drops? 

    Are you able to use I2C to communicate with the 949 with the HDMI connected or is it just the 948 that is unable to communicate?

    Can you share the value of register 0xC of the 949 before you connect the HDMI and after you connect the HDMI? 

    Best,

    Shu

  • hi Shu

    We can use I2C to communicate with the 949 with the HDMI connected but the 948 is unable to communicate.

    After HDMI connected  : register 0x0C ;  value :0x07

    Before HDMI connector: register 0x0C ;  value :0x01

  • Hi Kevin, 

    I will need some time to look into this, can you try to perform an HDMI reset by setting the 949 register 0x1 bit 4? Are you connecting the HDMI straight to the 949 after up and link to the 948 or have it connected prior to connecting to the 948? Can you share the power sequence? 

    Also note that Monday 7/4 is a holiday in the US and responses may be delayed. 

    Best,

    Shu