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DS90UH947-Q1: 947

Part Number: DS90UH947-Q1

Hi Expert ,

Several questions about 947 and 948, 

  1.  947 oLDI interface have 8 data lane and 1 clock lane while 948 have 8 data lanes and 2 clock lane, why the two OLDI interface is different?

For 947 side, the standard SOC oldi interface should contain 1 clock lane and 4 data lane. How if the SOC can not support 1 clock lane with 8 data lanes?

2. clock limit

the highest frequency of 947 clock limit is 96MHz @ single lance and 170MHz @ dual lane while the highest frequency of 948 clock limit is 96MHz @ single lance and 192MHz @ dual lane .

Why the 947 dual lane frequency is lower than 948 while single lane the same?

Thanks

Best regards,

David

  • Hi David, 

    Thank you for your questions.

    1.  The 948 device have functional modes that can either output single link or dual link OLDI. When in dual link configuration, the LVDS channels are split to carry even and odd pixel data (D0-D3 ODD, D4-D7 EVEN) therefore requiring individual clk signals for synchronization purposes. 

    2. Our IVI serializers and deserializers are interoperable within the FPD-Link IVI device family. The 948 can be paired with other serializers and the 947 can be paired with other deserializers. This is why the specifications are not an identical match. In this particular pairing the limitation would be on the serializer size and can only drive resolutions up to 170MHz PCLK. 

    Best,

    Best,

    Shu

  • Hi Shu,

    Does 947 can be configured to single link or dual link? 947 only have one clock, how can it be configured to dual oldi link?

    Thanks

    Best regards,

    David

  • Hi David, 

    On the 947 side, single vs dual link OLDI can be configured by setting the hardware strap mode listed in Table 7 in the 947 datasheet. 

    Let me know if this helps. 

    Best,

    Shu