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Original question:

[FAQ] SN65DSI84: How to configure the SN65DSI84 and SN65DSI85 for single channel DSI to dual channel LVDS

SN65DSI84: PLL doesn't lock - flicker on test image.

Theo Debrouwere
Prodigy 10 points
Part Number: SN65DSI84

The screen uses the following timings (dual link lvds):

clock = 74250, /* kHz */
horizontal active = 1920
horizontal front  =   20
horizontal sync   =  240
horizontal back   =   20
vertical active   = 1080
vertical front    =    2
vertical sync     =   41
vertical back     =    2

Using format 1, 24 bpp, DE+, HS-, VS-

I configured the mipi interface to use the same timings, 4 lanes, RGB888 - dsi clock A @ 445.5MHz

I use the dsi tool (see output below) & calculated everything by hand (resulting in the same register settings)

My issues:

  • Regular mode: I don't have an image. Only a black output on lvds. (though I can measure there is data on the mipi lines) Error register E5 shows 0x01 -> pll didn't lock. I don't know why the pll didn't lock. Mipi clock seems stable when I measure it.
  • Test image: There are bars visible on screen. I can measure the lvds clock, and it is correct. (74.xx Mhz) However, the screen flickers.

I included my settings in a tar file, since I can't upload a *.dsi file.

I'm not sure what is going wrong, or what I can try next. Can you spot any misconfiguration? Or give some clue to continue?

Thanks

files.tar

  • 0
    TI__Guru**** 177386 points

    Hi,

    Can you please share your schematic? Are you using the clock source from DSI CLOCK or reference clock? If using the DSI clock, can you change to a reference clock? When you say test image, are you referring to the test pattern being generated internally by the DSI84? If this is case, then the flicker image may come from the jitter of the DSK clock if you are using the DSI clock as your clock source.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 10 points

    I'll need to ask about the schematic. It's nothing fancy. mipi -> dsi84 -> lvds connector.

    We are using the DSI clock, but we can't change to a reference clock. The test image is the internally generated one.

    I attached another screen, but with a lower resolution. I didn't see any flickering on there. Is there a limit for the dsi clock?

  • 0 in reply to Theo Debrouwere
    TI__Guru**** 177386 points

    Hi,

    The DSI CLK range from 40 to 500MHz, so the 445.5MHz is still within the DSI CLK supported range. But with the internally generated test pattern also showing the flicking, I think the DSI CLK jitter is causing the issue here. This is why I want to try the reference clock or maybe cleaning up the DSI CLK jitter a bit to see if it will help with the flicking image issue.

    Thanks

    David