DP83826I: CLKOUT following POR starts 50 ms delayed

Hi Manual,

Can you capture the power ramp on the misbehaving DP83826?

PHY requires clock signal be given while power is ramping. Alongside the power ramp capture, please have reset and clock on same capture. 

Best,

Alon

Hi Alon, 

here is the capture. RST_N rises only to 2 V. On our board there is a 10k PD. 

Here is the same measurement without the 10k PD: 

The behavior is the same.

Hi Manuel,

As you can see, the clock signal starts after you begin power ramp. 

Clock needs to be present before beginning of power ramp. 

Why do you have a PD on RST? Why a 10k one?

Best,

Alon

Hi Alon,

We use a crystal that is driven by the Ethernet Phy DP83826 - XO Pin, We don't use a CMOS level oscillator. 

How can the clock be present before power up, if it is generated by the Ehternet Phy?

The crystal (directly connected to the Ethernet Phy) starts oscillating at power up. But the CLKOUT of the same Ethernet Phy starts.with a 50 ms delay.

Therefore it seems to be a misbehavior in the Ethernet Phy. 

Can you please tell me, what else controls the CLKOUT inside the chip?

Do you have a hardware architecture of the Phy (especially the CLKOUT function)?

The PD on RST is historically in the design, but has no effect on this behavior - as you can see above. 

Best regards,

Manuel

Hi Manuel,

Could you please provide us with the full schematic here?

We were under the impression you were using a crystal. Is the power supply used a common one for 3v3 and VDDIO?

If it only used for one of the supplies, could you please provide a scope capture of both supplies?

Best,

Alon 

Hi Alon, 

I've sent you the schematic.

We are using a crystal quartz.as shown in the upper picture of the schematic. 

We use a common power supply for 3V3 and VDDIO.

Best regards, 

Manuel

Hi Manuel, 

Gokul will continue with the debug here. 

Enjoyed working with you!

Best,

Alon