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DS90UB948-Q1: Power on sequence PDB RIN+/-

Jingjing Zhao
Prodigy 80 points

Part Number: DS90UB948-Q1

Hi, Expert

Some queries about DS90UB948-Q1 power on sequence during reading datasheet.

1. Does t4 is mandatory during power on for PDB?

2.  If t5 not satistied( RIN+/- data later than powered up), and without SW reset and hard rest during power on. what's the risk of it?

Thanks

Jingjing

  • 0
    TI__Mastermind 32990 points

    Hi Jingjing,

    1. Does t4 is mandatory during power on for PDB?

    • t4 wouldn't be relevant on the initial power-up/PDB assertion.
    • PDB pulse width (t4 - 2ms) needs to be met during a toggle event - it's a timing requirement for the PDB toggle.

    2. If t5 not satisfied ( RIN+/- data later than powered up), and without SW reset and hard rest during power on. what's the risk of it?

    • Typically we recommend powering up the deserializer after the serializer side of the link is active, so if t5 is not satisfied and no SW reset, you could end up locking to any random state or noise signal. The SW rest ensures ensures DS90UB948Q-Q1 has a deterministic startup behavior, specified lock time, and optimal adaptive equalizer setting.

    Regards,

    Fadi A.