Other Parts Discussed in Thread: DSI-TUNER
Hi team,
Does the delayed output HV signal relate to DSI83 caching more RGB data to FIFOs, can FIFOs hold a row of active data?
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Hi team,
Does the delayed output HV signal relate to DSI83 caching more RGB data to FIFOs, can FIFOs hold a row of active data?
Hi,
Are they using the DSI Tuner SW to generate the DSI83-Q1 register value? HS and VS signals are generated on the LVDS output after the delay programmed into register 0x28. The DSI-Tuner will configure these registers for them.
Thanks
David
Hi,
Correct, I would leave the value as set by the DSI Tuner SW.
Thanks
David