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DS32EL0421: DS32EL0421 TxClk Max Clock Jitter Specification for 3.125Gbps

ngrkus
Expert 1020 points
Part Number: DS32EL0421

Hi,

I need to figure out the max allowable clock jitter on the differential lvds clock input to guarantee proper PLL locking under all conditions for 3.125Gbps. How can I compute calculate this jitter/noise figure from the datasheet of the DS32EL0421?

br

Markus

  • 0
    TI__Guru 64326 points

    Hi Markus,

    I am looking into this and will let you know if I can provide this information.  

  • 0 in reply to Malik Barton57
    Expert 1020 points

    Hi Malik,
    do you have any news for me with respect to this? We do face link lochUps occassionally (30..90 Minutes) I wonder the root cause. The only solution is to power-cycle the transmitter receiver pair. Transmission is done over 10..12meter CAT5e cable.

    The datasheet does note that there is an internal biasing circuitry making sure the differential input is well balanced. I wonder if we face a receiver saturation effect, since the 10..12meter of shielded cables are dc-connected to the receiver. If an offset voltage is building up throughout the cabling, is it strong enough to overdrive the internal biasing network of the receiver?

    br

    Markus

  • 0 in reply to ngrkus
    TI__Guru 64326 points

    Hi Markus,

    During this failure have you tried stopping the LVDS link and then restarting without power-up? I agree this failure does seem to be some sort of common mode shift if the only way to recover  is to power cycle the system. Can you measure the Vcm of the link during normal operation vs. the failure condition? 

  • 0 in reply to Malik Barton57
    Expert 1020 points

    Hi Malik,
    I will try to measure. The equipement is not in my area. I will need some time to do the measurement. I will let you know the outcome once I get a chance to have the machine for this kind of measurements.

    In the meantime, since the transmitter is being driven by an ALTERA FPGA, I just wonder about the jitter specs. In the past I saw a few problems on the clients side using the FPGA as the driver for both the clock and the data. In some cases these serializer (like for example the TLK serie from TI) do have tight rms jitter specs for the clock that some of the FPGA's have difficulties to meet.

    br

    Markus

  • 0 in reply to ngrkus
    TI__Guru 64326 points

    HI Markus,

    Sounds good you can just reply here when ready. I suspect jitter may not be the main issue here however jitter can definitely effect the input here over long periods of time, measuring a bathtub curve of the data stream at input of  DS32EL0421 will tell us more.