DP83TC811R-Q1: Dangling RX_D3 pin do not strapped to MODE 1

Hi Edward,

What is the indication that RX_D3 is internally strapped to Mode4 instead of Mode1. Is it through register 0x467?

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Regards,
Gokul.

Hi Gokul,

      Thank you for your reply. Yes, it is through register 0x467 to read the Configuration of RX_D3.

Hi Edward,

Can you please provide me a register dump of 0x467,0x0000,0x0001?

Also, can you measure the pin voltage of RX_D3 (using a multimeter) when RESET_N pin is held low?

--
Regards,
Gokul.

Hi Gokul,

The information below is based on RX_D3 is open.  The register of 0x467 is 0x30ff.

 The pin voltage of RX_D3 (using a multimeter) when RESET_N pin is held low is 0.963V.

Hi Gokul,

Hi Edward,

I see that all the straps RX_D0,D1,D2,D3 and RX_DV are read Mode4. I suspect the host/MAC is driving them high when the device is in reset. Can you please depopulate the series resistances in the RX_D signal paths and check?

--
Regards,
Gokul.

Hi Gokul,

When I depopulate the series resistances in the RX_D signal paths,  the pin voltage of RX_D3 is 0V.

In addition, addr 0x0000 = 0x2100, addr 0x0001 = 0x61, addr 0x467 = 0x0000.

Hi Gokul,

Now I am looking into the  host/MAC. I try to assert the pin connected to RX_D3 of MAC pull down, the pin voltage of RX_D3 (using a multimeter) when RESET_N pin is held low is 0V. But the register of 0x467 is still 0x30ff. The waveform of RX_D3 and RESET_N is shown below(yellow is RESET_N and blue is RX_D3).

The waveform of RX_D3 and RESET_N when depopulate the series resistances in the RX_D signal paths is shown below. The register of 0x467 is  0x0000.

As shown in the datasheet, hardware configuration latch-in time from reset within 700ns. I thought the register of 0x467 should not be 0x30ff, since both waveforms of above are the same within 700ns.

When RX_D3 pin pull down with 2kΩ, the waveform of RX_D3 and RESET_N when depopulate the series resistances in the RX_D signal paths is shown below.

Hi Edward,

To understand the difference with and without depopulating the series resistors, I suggest zooming in the above waveforms to scale of 200-300ns and observe how signals are behaving.

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Regards,
Gokul.

Hi Gokul,

The waveforms with series resistors is shown below. During the 200ns after reset signal rises, there is 100mV in RX_D3.

The waveforms without series resistors is shown below. During the 200ns after reset signal rises, there is 0mV in RX_D3.

Would this 100mv affect the registers 0x467?

Hi Edward,

Did the voltage become 100mV now after a change?

100mV should be okay. Can you please read the strap register now and check if it is reading correctly now?

--
Regards,
Gokul.

Hi Gokul,

The register of 0x467 is still 0x30ff. I think it is not correctly.

Hi Edward,

Can you please send me the zoomed out waveforms and zoomed in waveforms together? It is strange that even if the voltage is low, the register is still reading 0x30ff.

The zoomed out waveforms show that the voltage is stuck at a mid voltage, but that's not the case in zoomed in waveforms. I suggest capturing the waveforms again to resolve this discrepancy.

--
Regards,
Gokul. 

Hi Gokul

    I zoomed in the red rectangle of the waveforms. The duration between the rising edge of the yellow and  blue waveforms  is 172us, so the stuck voltage did not show in the zoom in waveforms. The yellow waveform is the reset signal, I think the hardware configuration latch-in time from reset within 700ns and I just zoomed in the red rectangle. Should I provide the 172us stuck voltage zoom in waveform?

Hi Edward,

We want to look at the behavior between rise edge of RESET_N and fall edge of RX_* line (Closer to line AX in the above image)
Can you please check if the behavior is same across all RX_* pins?

--
Regards,
Gokul.

Hi Gokul

 The behavior between rise edge of RESET_N and fall edge of RX_* line (Closer to line AX in the above image) is shown blow.

And I disconnected the series resistance of MCU and PHY, the waveform of RX_* line (Closer to MCU) is shown blow.

And this MCU can't change Power-up characteristics that power on is high level. I am looking into the host/MAC side now.