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DS90UB941AS-Q1: use external clock make screen shakes

Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: LMK05318B

Ds90ub941 displays normally when using DSI clock, but displays jitter when using external clock.

The register is configured 0x56 = 0x01

  • Hello,

    What is the DSI PCLK rate and what is the frequency of the REFCLK?

    Best Regards,

    Casey 

  • Hi,Casey

    this is DSI PCLK

    REFCLK is 180.25MHz too,it's created from lmk05318b 

  • Monkey,

    Ok, interesting - can you please send your full video timing parameters along with the script you are using to initialize 941AS?

    Best Regards,

    Casey 

  • XO =24.000 MHz, CH4 = 25 MHz, CH5 = 180.25 MHz.tcs

    this is lmk05318b configurations

                writeLvdsRegister(0x01,8);
                writeLvdsRegister(0x56,1);
                writeLvdsRegister(0x01,0);
    this is my program to initialize 941AS,only change BRIDGE_CLK_MODE,Is there any more register they need to change
  • I tried this to eliminate jitter

                writeLvdsRegister(0x40,0x04);
                writeLvdsRegister(0x41,0x20);
                writeLvdsRegister(0x42,0x6F);       // DSI_CONFIG_0

                writeLvdsRegister(0x41,0x31);       //DSI_HSYNC_WIDTH_LO
                writeLvdsRegister(0x42,26);
               
                writeLvdsRegister(0x41,0x33);       //DSI_VSYNC_WIDTH_LO
                writeLvdsRegister(0x42,2);
               
                writeLvdsRegister(0x41,0x35);       //DSI_SYNC_DELAY_LO
                writeLvdsRegister(0x42,10);
  • Hello,

    Are you saying that overriding the sync widths fixed the jitter or no?

    Can you try running PATGEN with internal timing and external clock to see what result this has on the screen? 

    If that works correctly, then please try PATGEN with external timing and external clock. Basically follow this flow chart to see where it breaks:

    Are you using DSI burst mode or non-burst mode? Are you using sync events or sync pulses from the DSI source side?

    Can you also share the full timing? We may need to add at least TSKIP_CNT configurations to your 941AS script at minimum. If you can send me the info above then I can help make sure you have the right 941AS configs

    Best Regards,

    Casey 

  • Hi,

    1. Overriding the sync widths couldn't fixed the jitter.

    2. try PATGEN with internal timing and external clock,video is ok

    3. try PATGEN with external timing and external clock,video is jitter

    4.  read DSI_VC_DTYPE Register = 0x3E,does it right?

    5. I'm not sure what kind of DSI mode we are currently using,I will check with who in charge with it.

    6. This is the screen parameter

    Display:                          ((hactive + hsync + hbp + hfp) * (vactive + vsync + vbp + vfp) * frame-rate)
    15 inch(2240*1260):       ((2240    + 26    + 68  + 24)) * (1260    + 2     + 6   + 6  ) * 60,0      ) = 180,245520 Hz
    we use DSI0 input,4 lines,Auto-Detect FPD-Link III mode
  • Hello,

    My best guess here based on the data provided is that the sync widths are not getting regenerated in the DSI stream with correct timing. It may require some deeper analysis of the DSI stream with an analyzer to see what is happening. See section 4.3 of this app note for detail https://www.ti.com/lit/pdf/snla356

    Best Regards,

    Casey