Other Parts Discussed in Thread: DP83849I
From the DP83826E datasheet:
"Up to 8 PHYs can share a common SMI bus. To distinguish between the PHYs, during power up or hardware
reset, the DP83826 latches the Phy_Address[2:0] configuration pins to determine its address."
Are there any example schematics or block diagrams for this architecture?
I have a single MII/RMII/RGMII interface that I need to connect to two separate ethernet output ports and I'm wondering if the DP83826E will meet my needs.
Thank you and best regards,
Jessica