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DP83867IR: TX operation not performed

Part Number: DP83867IR

Current status :
1. RGMII with 1000Mbps
2. Register Read/Write operation: PASS
3. After connecting with LAN cable, I try to test with my simple UDP program or ping, then, pins related to AVB-TX do not work.

After the LAN cable is connected, the values of the registers read in the boot step are as follows.

Address

Register Name

Register Value

0x0000

BMCR

0x1140

0x0001

BMSR

0x796d

0x0002

PHYIDR1

0x2000

0x0003

PHYIDR2

0xa231

0x0004

ANAR

0x1e1

0x0005

ANLPAR

0xc5e1

0x0006

ANER

0x6f

0x0007

ANNPTR

0x2001

0x0008

ANNPRR

0x6801

0x0009

CFG1

0x300

0x000A

STS1

0x3800

0x000B

 

 

0x000C

 

 

0x000D

 

 

0x000E

 

 

0x000F

KSCR1

0x3000

0x0010

PHYCR

0x5048

0x0011

PHYSTS

0xac02

0x0014

CFG2

0x29c7

0x0017

STS2

0x40

0x001E

CFG3

0x2

0x0031

CFG4

0xac02

0x0032

RGMIICTL

0xd3

0x0033

RGMIICTL2

0x0

0x006E

STRAP_STS1

0x5

0x006F

STRAP_STS2

0x110

0x0086

RGMIIDCTL

0x57

0x00C6

PLLCTL

0x0


Please let me know if there is anything else I need to check.

  • Hello,

    It appears that you do have link which is leading to me believing that the issue lies in the RGMII interface. A common issue is that the RGMII delays are not implemented properly. Please try playing around with Reg 0x86 bit fields to see if there is a working combination to be had.

    Sincerely,

    Gerome

  • Thanks for your reply.

    I set some values into RGMIIDCTL(0x86) register using mmd.

    But, Tx signals still do not work.

    I think the main issue is that TXC(tx clock) is not output from our board(MAC).

    The OS driver is provided by GHs (GreenHills Integrity RTOS).

    They told me that other customers already used the provided OS driver and I have no need to add code except to add PHY ID.

    Could you please let me know what to look for TXC? H/W or S/W?

  • Hello,

    According to the datasheet, TX_CLK (known as GTX_CLK in the pin configuration) shall be 125MHz. It also goes from 0 to VDDIO.

    Sincerely,

    Gerome

  • Thanks for your response.
    I think there is nothing wrong with the 125MHz reference clock resource because my board is normally working with other PHY IC as KSZ9031.
    I will tell you about my test environment, it will help you to understand.

    <<Test envrionment>>
    1. H/W
       (1) My Board with KSZ9031 Phy IC 
       (2) My Board with DP83867 Phy IC

    2. S/W
     (1)  Exactly the same.

    3. Result
    KSZ9031 Phy IC is normal working, but DP83867 Phy IC isn't. No TXC ouput signal.

  • Hello,

    TX_CLK is an input for the device. As such, our team does not have insight as to why the signal is not showing up on the line. For this to be resolved, you need to contact the team behind the MAC to understand why TX_CLK is not being activated.

    Sincerely,

    Gerome