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DP83822I: doesn't work 100 mbps only 10 mbps

Part Number: DP83822I

Hi all,

we are using DP83822I with zynq 7020 in buildroot linux environment. the kernel version is 4.14. The interface between zynq and this chip is rgmii-id. following attachment is the schematic of the circuit

this is the devicetree.dts configuration

&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@1{
reg = <0x1>;
device_type = "ethernet-phy";
};
};


zynq-7000 dtsi

        gem0: ethernet@e000b000 {
            compatible = "cdns,zynq-gem", "cdns,gem";
            reg = <0xe000b000 0x1000>;
            status = "disabled";
            interrupts = <0 22 4>;
            clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
            clock-names = "pclk", "hclk", "tx_clk";
            #address-cells = <1>;
            #size-cells = <0>;
        };

the kernel is picking up the driver successfully and eth0 is visible in the ifconfig


However, it only works at 10mbps/full mode only, even though the router which is connected to ethernet port can operate up to 1g and all other devices operate in trimode, this phy chip can't go beyound 10 mbps and upto 100 mbps.

this is the mii info from uboot

any advise would be highly appreciated.
thanks,

Hasila

  • Hi Hasila, 

    Can you try connecting this board to other link partners? Is the same behavior seen?

    Please send me a register dump with device linked up in 10mbps, including registers 0x467 and 0x468.

    Thanks,

    David

  • Hi David,
    yes I tried with other routers as well, it is exactly the same behavior. this is the ethtool dump of eth0

    I tried to access to the register 0x467 and 0x468 but in the mii and  mdio doesn't support for accessing for these registers since they are beyond the normal address range. If you are concerned about the pull status of the rx pins, this is the zynq configuration for the mii interface

    thanks.

    Hasila

  • Hi Hasila, 

    I am not seeing how the image you sent corresponds to the register reads. Register 0x0002 should have value 0x2000 and register 0x0003 should have value 0xA240. I do not see these numbers anywhere in your screenshot. Can you explain what you have sent?

    Registers 0x467 and 0x468 will show that the device is strapped in the correct mode. They are extended registers, so you must use the procedure listed in section 8.4.2.1 of the datasheet to read these.

    Thanks,

    David

  • Hi David,

    these are the 0x2 and 0x3 register value from uboot

    any idea why they are like that but  does the values appear  in mii info correct?

    thank you,

    kind regards,

    Hasila

  • Hi David,

    I was able to read the register at 0x467 and 0x468 in the uboot. it looks like RX_D0 is in mode3, that's why I think it has shown wrong values in the ethtool with linux, because devicetree was set to 0x1 at that time. can I change the AN_1 to 1 in software by using ethtool or using uboot mii commands. could you please tell me how

    Thank you,

    Kind regards,

    Hasila

  • Hi Yasitha,

    You can write bit 12 of register 0x0000 to a 1 to override the strap value. I am only familiar with the phytool commands in linux, which have the following format:

    phytool write Interface/PHYID/Register WriteValue

    In your case, it would look like this:

    phytool write eth0/3/0x0000 0x3100

    Thanks,

    David

  • Hi David,

    I used the phytool as you sugessted in the linux environment, and set the resister 0x0 to 0x3100, but it is the same, not picking up 100 mbps

    Thanks,

    Hasila

  • Hi David,

    Do I have to use pull up resistors on the RX pins in order to stabilize the interface between zynq and this chip

  • Hi Hasila, 

    Pull up resistor is not required on the rx pins if they are not used for strapping. See the default strapping values in table 8-10 of the datasheet. 

    Please send me a complete register dump from 0x0 to 0x1F. 

    Thanks,

    David

  • Hi David, Please find the attachment for the all the dump I have done with the mii commands in uboot.

    Register dump from 0 to 1f using mii dump.pdf

  • Hi Hasila, 

    You are not using the correct syntax to read registers in u-boot. Values of 0xFFFF indicate a failed read. See the following image: 

    Please use the mii dump command to read registers 0-5, then the mii read command to read registers 0x5 through 0x1f.

    I would also like to see the values of registers 0x467 and 0x468, but note these are extended registers, so you must follow the procedure listed in section 8.4.2.1 of the datasheet.

    Thanks,

    David

  • Hi David,

    I am not quite sure why you are asking to read the registers through 0x1f. It is quite clear that the chip is talking in 0x1 address and based on the schematic I provided, it must be sit at address 0x1. These are the dumped values of register from 0-5. and I also read the value of 0x5 through 0x1. I read the section 8.4.2.1 of the datasheet. It is not quite clear to me how to access to the extended register, using mii in uboot or any other method and I don't have the IEEE standard for 802.3ah clause 22. since we are already paying for this chip and you guys have made this chip I expected better resolution in this  matter from your side. If you are not sure about this could you please ask from internal expertise regarding this matter.

    thanks

    have a great day

    Hasila

  • Hi Hasila,

    From your most recent image, I can see that auto-negotiation was completed and link is up. I can see the DP83822 is advertising 100Mbps ability in register 0x4.

    Looking at register 0x5, however, I see your link partner is not advertising 100Base-Tx operation. You will not get a 100Mbps link if the link partner does not have this ability or is not advertising it. 

    Please fix this on the link partner side, or try connecting to a different link partner. 

    Thanks,

    David

  • Hi David,

    what you are saying doesn't make any sense at all. I have tested this chip with a direct router with very short ethernet cable, with a switch and one another router that we dont use. all these devices can successfully operate at 10/100 or 1000 mbps and intact this is not the only chip that operate at 100 mbps we have other development boards that also work at 100 Base-Tx. I am not wasting time and energy by replying fallacy. So far my observation is the interface between ZYNQ and the DP83822I messes the bootstrap configuration regarding 10mbps and100 mbps as discussed in 8-11 table. Could you please address how to tackle when this happen with this chip.

    Hasila

  • Hi Hasila,

    If you would like, we can confirm your suspicion of the ZYNQ messing with the bootstrap configuration by reading registers 0x467 and 0x468. 

    The solution to this issue is to high-z the pins of the ZYNQ which are connected to the PHY until after the Hardware configuration latch-in time for power up spec in the datasheet (200ms).

    Alternately, if the ZYNQ is being powered up at the same time as the PHY, you can try resetting the PHY after they are both powered on. 

    Thanks,

    David

  • Hi David,

    I tried your way. It doesnt work. However, when I leave the ethernet cable connected for a long time, I get this message that link is up at 100 full but imediately it goes to link down, it just keep connecting and disconnectin like every three minute or smoething.

    then I tried to turn off the auto negotiation with ethtool command as follow. it is the same connection just keep connecting and disconnection quite fast.

    Then I change the speed to 10 mbps and let the auto negotiation on . then It connect successfully and does not disconnect. what kind of things could causes for this kind of behavior?

    thanks

    Hasila

  • Hi Hasila,

    This behavior can hint of a signal integrity issue, since the link is not able to be sustained at 100Mbps, but it solid at 10Mbps. This can be due to a layout issue, component issue, faulty cable, etc.

    Here are a few things to check:

    1. Please ensure the oscillator is meeting the following specs:

     

    2. What magnetics are you using?

    3. Is fast link drop enabled? Check this in register 0x000B. Try disabling it if so.

    4. Send me the reading of registers 0x467 and 0x468.

    Please refer to the PHYTER Design & Layout GuideDP83822 IEEE 802.3u Compliance and Debug, and Ethernet PHY PCB Design Layout Checklist for more information.

    Thanks,

    David

  • Hi David,

    1. the oscillator we are using even better than your evaluation board. it is ASDMB-25.000MHZ-LC-T
    2. this is the link for the magnet we are using

    3.fast link is disabled.

    4. the values of these registers have been shared many posts above

  • Hi Hasila,

    I will review the information and check with the team and get back to you with some ideas.

    Thanks,

    David

  • Hi Hasila,

    Please send me a comprehensive and searchable schematic to review. 

    Thanks,

    David