DS90UB954-Q1: DS90UB954-Q1 POC S parameter fail

Hello Elec,

There are a number of reasons why the Channel Specifications are not being met in your specific customer system, most of which are due to either issues with the PCB layout or components along the high-speed FPD-Link channel. 

1. Can you use a TDR and verify that the single-ended impedance along the entire FPD-Link path is 50-Ohms (+/-10%)?
   1. You can also use a TDR to measure the impedance on the cable and each PCB board, to see if there is a specific component that is causing excessive impedance mismatch.
2. Parasitic load capacitance along the high-speed signal trace will also affect the signal integrity. 
   1. Have you investigated if anything along the high-speed signal trace introduces excessive load capacitance?
3. There are also a variety of layout guidelines that should be followed, in order to make sure that the S-Parameter Channel Specifications can be met, such as adding anti-pads underneath landing pads of components along the high-speed trace, in order to minimize impedance mismatch and parasitic capacitance, route high-speed traces using rounded corners or >135 degree turns, etc...
   1. Would you be able to provide the layout, so that I can review in more detail?

Best,

Justin Phan

Hi Justin,

I am asking for the layout from the customer.

What's TDR? Do you have guide for that? Thanks.

Justin Phan said:

Can you use a TDR and verify that the single-ended impedance along the entire FPD-Link path is 50-Ohms (+/-10%)?

BR,

Elec Cheng

Hello Elec,

TDR stands for Time-Domain Reflectometer and is a lab equipment that can be used to measure the impedance along a cable or PCB trace. We do have detailed guides on how to take these types of measurements, but those documents are under NDA.

If your customer is under NDA with TI and you can help provide the relevant information, so that I can look it up in our NDA system, then I can provide the documents.

Best,

Justin Phan